DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 6/27/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 31-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20230096214 A1 (Lee et al hereinafter Lee).
Regarding claim 31, Lee discloses a method for forming a semiconductor device structure (a method to form the device of FIGS. 1-3 ¶ [0010-0012]), comprising: forming a first dielectric material layer (FIG. 3, source line insulating layer 122 is formed ¶ [0041]) over a substrate (FIG. 3, substrate 110 is formed ¶ [0034]); forming metal lines (FIG. 3, source lines SL, excluding for a portion contacting channels 160, are formed in layer 122 ¶ [0035]) in the first dielectric material layer; forming a two-dimensional array (FIG. 2, memory cell array MCA is formed ¶ [0033-0034]) of semiconductor channels (FIG. 3, channel layers 160 ¶ [0048]) and bottom electrodes (annotated FIG. 3 below, segments of source lines SL contacting channels 160 function as bottom electrodes in an array) over the metal lines; forming a ferroelectric dielectric layer (FIG. 3, ferroelectric layer 152 is formed and surrounds channels 160 ¶ [0055]) surrounding the semiconductor channels;
forming an electrode material layer (FIG. 3, horizontal extension portions 140E are formed over sidewalls of ferroelectric layer 152 ¶ [0046]) over the ferroelectric dielectric layer; forming a metal layer (FIG. 3, main gate portions 140M surround channels 160 ¶ [0046]) surrounding the semiconductor channels; forming top electrodes (FIG. 3, bit line contacts 168 are formed on channels 160 ¶ [0057]) on the semiconductor channels; and forming conductive features (FIG. 3, bit line BL are formed over bit line contacts ¶ [0057]) over the top electrodes, wherein the conductive features serve as bit lines.
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Regarding claim 32, Lee discloses the limitations of claim 31 as detailed above and further discloses that each semiconductor channel comprises InGaZnO (IGZO) (channels 160 may be formed of IGZO ¶ [0056]) and the ferroelectric dielectric layer comprises hafnium zirconium oxide (HZO) (ferroelectric layer 152 may be form of hafnium zirconium oxide “Hf.sub.xZr.sub.1−xO.sub.y (0.2≤x≤0.8 and 2≤y≤4)” ¶ [0055]).
Regarding claim 33, Lee discloses the limitations of claim 31 as detailed above and further illustrates steps (FIGS. 13-22 show a step-by-step process for forming device 100 of FIG. 3 ¶ [0022, 0099]) forming a first etch stop layer (FIG. 14, first insulating layer 130 functions in a capacity to stop an etch, and is formed on source insulating layer 122 ¶ [0101]) on the first dielectric material layer before forming the ferroelectric dielectric layer (ferroelectric layer 152 was not yet formed in the step of FIG. 14); and forming a second etch stop layer (FIG. 22, fourth insulating layer 166 is formed after gate electrode 140 ¶ [0118]; layer 166 functions in the capacity of stopping an etch) after forming the metal layer and before forming the top electrodes (FIG. 22, it is stated that bit line contacts 168 are formed after layer 166 is formed by forming openings in layer 166 and filling the openings with conductive material to form contacts 168 ¶ [0118]).
Claims 36 and 38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20230253351 A1 (Wang et al).
Regarding claim 36, Wang discloses a method for forming a semiconductor device structure, comprising: providing a first interconnect structure (FIG. 2, front-side interconnect structure 30 ¶ [0017]) over a first side (FIG. 2, the upper side designated ‘front-side’ ¶ [0017]) of a device layer (FIG. 2, device layer 26 and substrate 22 ¶ [0016]), wherein the first interconnect structure comprises a first array (FIG. 2, front side memory elements 36 may be an array of non-volatile FeRAM cells ¶ [0019]) of non-volatile memory cells; attaching the first interconnect structure to a carrier substrate (FIG. 3, carrier wafer 60 attaches to front-side interconnect structure 30 ¶ [0029]);
flipping the carrier substrate (device is flipped subsequent to carrier substrate being attached to expose TSVs 90 to further processing ¶ [0036]) such that a second side of the device layer is facing up to expose a backside of the device layer (FIG. 3, the lower side of substrate 22 is a backside); removing a portion of a substrate of the device layer from the backside (FIG. 4, a portion of substrate 22 is removed from its lower side, designated ‘back-side’ ¶ [0036]); forming a memory device layer (FIG. 5, back-side memory elements 126 are formed in a memory device layer which is over substrate 22’s backside ¶ [0041]) over the backside of the device layer, wherein the memory device layer comprises a second array of non-volatile memory cells (FIG. 5, back-side memory elements 126 may be an array of non-volatile memory cells ¶ [0041]); and providing a second interconnect structure over the memory device layer (FIGS. 6A-6B, some conductive features 124 are provided over back-side memory elements 126, such as the feature designated ‘M4’ in FIG. 6B ¶ [0040]; additionally, UBMs 130 and conductive bumps 140 provide interconnections ¶ [0048]).
Regarding claim 38, Wang discloses the limitations of claim 36 as detailed above and further discloses that non-volatile memory cells of the first array are different from non-volatile memory cells of the second array (FIG. 5, memory element structures 36 and 126 are different at least in the sense that they differ in location in the device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 19, 21, 23, and 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20230253351 A1 (Wang et al hereinafter Wang) in view of US 20210074725 A1 (Lue).
Regarding claim 19, Wang discloses a method for forming a semiconductor device structure, comprising: providing a first interconnect structure (FIG. 2, front-side interconnect structure 30 ¶ [0017]) over a first side (FIG. 2, the upper side designated ‘front-side’ ¶ [0017]) of a device layer (FIG. 2, device layer 26 and substrate 22 ¶ [0016]), wherein the device layer has a substrate comprising one or more logic devices (FIG. 1, active and passive devices connected with TSVs 90 in substrate 22 may form one or more logic devices ¶ [0016]); attaching the first interconnect structure to a carrier substrate (FIG. 3, carrier wafer 60 attaches to front-side interconnect structure 30 ¶ [0029]); flipping the carrier substrate (device is flipped subsequent to carrier substrate being attached to expose TSVs 90 to further processing ¶ [0036]) such that a second side of the device layer is facing up to expose a backside of the substrate (FIG. 3, the lower side of substrate 22 is a backside);
removing a portion of the substrate from the backside (FIG. 4, a portion of substrate 22 is removed from its lower side, designated ‘back-side’ ¶ [0036]); forming a dielectric material layer (FIG. 5, second dielectric layers 122 are formed over backside of substrate 22 ¶ [0040]) over the backside of the substrate, wherein the dielectric material layer comprises a power rail coupling to a power supply (FIG. 5, back-side interconnect structure 120 includes “a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit” ¶ [0040]); forming a memory device layer (FIG. 5, back-side memory elements 126 are formed in a memory device layer which is over a layer-portion of second dielectric layers 122 which are between memory elements 126 and substrate 22) over the dielectric material layer, wherein the memory device layer comprises an array of memory cell devices (FIGS. 6A-6B, back-side memory elements 126 may be a memory array ¶ [0040]); and providing a second interconnect structure (FIGS. 6A-6B, some conductive features 124 are provided over back-side memory elements 126, such as the feature designated ‘M4’ in FIG. 6B ¶ [0040]; additionally, UBMs 130 and conductive bumps 140 provide interconnections ¶ [0048]) over the memory device layer.
Wang did not explicitly disclose that the array of memory cell devices was vertical-type, particular details of the memory array not being an element of emphasis in the disclosure of their invention. Wang does mention that the back-side memory elements may be non-volatile memory such as FeRAM (¶ [0041]).
However, Lue discloses a memory array structure which includes vertical type GAA FeRAM structures (FIGS. 1-2 illustrate vertical-type GAA FeRAM structures ¶ [0013-0014]), and Lue also teaches that their disclosed FeRAM structures “can operate with low power and high speed, with program and erase operations resistant to over-erase and over-program conditions” and can be implemented in high-density integrated circuits(¶ [0011]).
Wang and Lue both pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Wang in view of Lue such that the array of memory cell devices is vertical-type, in order to implement memory structures that can operate with low power and high speed, with program and erase operations resistant to over-erase and over-program conditions in the device of Wang, as taught by Lue.
Regarding claim 21, Wang in view of Lue disclose the limitations of claim 19 as detailed above, and Lue further discloses that each vertical-type memory cell device is a gate-all-around (GAA) structure (Lue FIGS. 1-2, the memory cells are in GAA structures ¶ [0014]) having a channel region (FIGS. 1-2, vertical channel structure 150 ¶ [0028]) surrounded by a ferroelectric material layer (FIGS. 1-2, ferroelectric memory material 115 surrounds channel 150 ¶ [0031]), and the channel region is vertically disposed between a top source/drain feature and a bottom source/drain feature (FIG. 1, bit line 147 functions as a drain feature ¶ [0070], and it can be seen in the circuit view of FIG. 10 that a source feature common source line CSL is arranged below the channel region ¶ [0067]).
Regarding claim 23, Wang in view of Lue disclose the limitations of claim 21 as detailed above, and Lue further discloses that each vertical-type memory cell device is a one-transistor (1T) FeRAM device (Lue FIG. 1, the elements forming upper transistor 110T make a 1T FeRAM device ¶ [0031]; it is not stated that the overall device consists solely of one transistor).
Regarding claim 25, Wang in view of Lue disclose the limitations of claim 19 as detailed above, and Lue further discloses that the array of vertical-type memory cell devices comprises at least two vertically stacked gate-all-around (GAA) structures (Lue FIGS. 1-2, each instance of the memory structure includes two vertically stacked GAA structures – select gate conductor 120 is formed around region 153 of the channel, and word line conductor 110 is formed around region 152 of the channel ¶ [0029-0030]).
Regarding claim 26, Wang in view of Lue disclose the limitations of claim 19 as detailed above, and Lue further discloses forming a bit line (Lue FIG. 1, bit line 147 is formed and coupled to the GAA structure ¶ [0047]) coupled to the array of vertical-type memory cell devices and extending along a first direction (in the view of FIG. 1, bit line 147 extends along a horizontal direction); and forming a word line (Lue FIG. 1, word line conductor 110 is formed ¶ [0029]) extending along a second direction that is different from the first direction (in the circuit view of FIG. 10, is can be seen that the bit lines BL0/BL1 and word lines WL have non-parallel main-extension directions), wherein the word line surrounds each vertical-type memory cell device (FIGS. 1 and 10, word line conductor 110 surrounds region 152 of the channels in a given row).
Regarding claim 27, Wang in view of Lue disclose the limitations of claim 26 as detailed above, and Lue further discloses that the first direction is perpendicular or non-perpendicular to the second direction (Lue FIG. 10, the first and second directions that the bit lines and word lines have their main extensions along may be either perpendicular or non-perpendicular to each other).
Regarding claim 28, Wang in view of Lue disclose the limitations of claim 19 as detailed above, and Wang further discloses that the attaching the first interconnect structure to the carrier substrate comprises bonding the first interconnect structure to the carrier substrate through a hybrid bonding process (Wang ¶ [0029], hybrid bonding may be used to attach carrier substrate 60 to device 20).
Regarding claim 29, Wang in view of Lue discloses the limitations of claim 19 as detailed above, but it is not explicitly stated that the removing the portion of the substrate from the backside comprises a thinning process performed until a portion of source/drain regions of the one or more logic devices is exposed. However, the thinning process of Wang does expose TSVs 90 (Wang ¶ [0014]). A person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to have the TSVs connect to source and drain elements of the logic devices, and themselves function in a capacity as extensions of the source/drain regions of the logic devices, in order to provide electrical connection from source/drain elements of the logic devices in the device layer 26 to the back-side interconnect structure 120 (FIG. 5), which can for example provide “a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit” (Wang ¶ [0040]).
Regarding claim 30, Wang in view of Lue discloses the limitations of claim 19 as detailed above, and Wang further discloses forming conductive features in the dielectric material layer (FIG. 5, fourth conductive features 124 are formed in second dielectric layers 122 ¶ [0040]), but did not explicitly state that the conductive features electrically connect source/drain regions of the one or more logic devices to the power rail.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to have the TSVs connect to source and drain elements of the logic devices, and themselves function in a capacity as extensions of the source/drain regions of the logic devices, in order to provide electrical connection from source/drain elements of the logic devices in the device layer 26 to the back-side interconnect structure 120 (FIG. 5), which can for example provide “a back-side power delivery network to provide the means of delivering power and other external connectivity to the integrated circuit” (Wang ¶ [0040]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lue as applied to claim 19 above, and further in view of US patent publication US 20210375888 A1 (Lu et al hereinafter Lu).
Wang in view of Lue discloses the limitations of claim 19 as detailed above, and Wang further discloses that device layer comprises one or more logic devices (Wang FIG. 1, active and passive devices connected with TSVs 90 in substrate 22 may form one or more logic devices ¶ [0016]), but they do not further disclose that each logic device is a planar field effect transistor (FET), a three-dimensional fin-like FET (FinFET), a gate-all-around (GAA) FET, a forksheet FET, or a complementary FET (CFET), particular details of the logic device structures not being features of emphasis in their disclosed invention.
However, Lu discloses a method of forming a memory device (a method to form the device of FIGS. 2-29E ¶ [0006]) wherein a device layer (FIG. 2, substrate 50 and the devices located on it, formed of elements 302, 304, 306, 308, 310, 312, 314, 320, and 324 ¶ [0025-0026]) may include transistors which may be “fin field effect transistors (FinFETs), nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) FETs (nano-FETs), planar FETs, the like, or combinations thereof” (¶ [0025]).
Wang, Lue, and Lu all pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would therefore find it obvious to modify the device of Wang in view of Lue further in view of Lu by using FinFETs or GAA FETs as the logic devices in the device layer of Wang, as those types of transistors have been demonstrated as suitable for inclusion in a device layer by Lu, for the purpose of managing space and optimizing the device density.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lue as applied to claim 21 above, and further in view of US patent publication US 20210399052 A1 (Wu et al hereinafter Wu).
Wang in view of Lue discloses the limitations of claim 21 as detailed above, and they further disclose that the ferroelectric material layer comprises hafnium zirconium oxide (HZO) (ferroelectric material 115 can be zirconium-doped hafnium oxide Lue ¶ [0031]), but they do not explicitly disclose that the channel region comprises InGaZnO (IGZO), a material of the channel region not being a feature of particular importance to the disclose of their invention.
However, Wu discloses a method of forming a semiconductor device structure (the method of forming the device of FIG. 13A-13E ¶ [0005]) wherein a channel region (FIG. 8A, channel region 110 ¶ [0035]) may be formed of IGZO (¶ [0035]).
Wang, Lue, and Wu all pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would therefore find it obvious to modify the device of Wang in view of Lue further in view of Wu such that the channel region comprises InGaZnO (IGZO), in order to provide a known material for the channel region which may be found beneficial from consideration of materials costs and changing market conditions.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lue as applied to claim 19 above, and further in view of US patent publication US 20230096214 A1 (Lee et al hereinafter Lee).
Wang in view of Lue discloses the limitations of claim 19 as detailed above, and they further disclose forming a two-dimensional array of semiconductor channels (Lue FIG. 1, vertical channel structures 150 are formed ¶ [0028-0029]) over the metal lines; forming a ferroelectric dielectric layer over the semiconductor channels (FIG. 1, ferroelectric layer 115 is formed on sidewalls of channel 150); forming an electrode material layer (FIG. 1, the portion of word line conductor 110 formed within the indicated transistor 110T structure over sidewalls of ferroelectric layer 115 is an electrode material layer ¶ [0031]) over the ferroelectric dielectric layer; forming a metal layer (FIG. 1, remaining portions of word line conductor outside the indicated transistor 110T structure are formed over sidewalls of the portions within the indicated transistor 110T structure; Lue discusses using a metal material such as tungsten to form the word lines, which a person of ordinary skill in the art before the effective filing date of the claimed invention would find obvious for providing a conductive word line structure ¶ [0056]) over the electrode material layer; and forming top electrodes (FIG. 1, contact plugs 148, which function as top electrodes, are formed on channels 150 ¶ [0029]) on the semiconductor channels.
Wang in view of Lue do not explicitly disclose forming metal lines in a first dielectric material layer, or that the two-dimensional array includes bottom electrodes; in contrast, Lue uses a configuration wherein a doped well functions in the capacity of a reference conductor (FIG. 1, reference conductor 149 may be n-type doped over p-type doped semiconductor body 100 ¶ [0028]) to provide a source region for the vertical-type GAA transistor structures (FIG. 10, see common source lines CSL of the circuit diagram ¶ [0068]), though Lue does mention that the reference conductor may be any suitable conductive material (¶ [0028]).
However, Lee discloses a method for forming a semiconductor device structure (a method to form the device of FIGS. 1-3 ¶ [0010-0012]), comprising: forming a first dielectric material layer (FIG. 3, source line insulating layer 122 is formed ¶ [0041]) over a substrate (FIG. 3, substrate 110 is formed ¶ [0034]); forming metal lines (FIG. 3, source lines SL, excluding for a portion contacting channels 160, are formed in layer 122 ¶ [0035]) in the first dielectric material layer; forming a two-dimensional array (FIG. 2, memory cell array MCA is formed ¶ [0033-0034]) of semiconductor channels (FIG. 3, channel layers 160 ¶ [0048]) and bottom electrodes (annotated FIG. 3 reproduced below, segments of source lines SL contacting channels 160 function as bottom electrodes in an array) over the metal lines. A person of ordinary skill in the art before the effective filing date of the claimed invention would also recognize the configuration having a metal line formed in a dielectric layer, set on a substrate as demonstrated in Lee to be a known alternative to the doped well conductor of Lue, which may be found beneficial in consideration of materials costs and changing market conditions, as well as electrical properties such as insulation protecting against parasitic capacitance, as Lue contemplated other suitable conductors may be used in their device.
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Wang, Lue, and Lee all pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Wang in view of Lue further in view of Lee to substitute the metal line in a dielectric layer configuration of Lee in place of the doped well of Lue, and in so doing include steps of forming a first dielectric material layer over a substrate; forming metal lines in the first dielectric material layer, and forming bottom electrodes over the metal lines, as Lee demonstrated a known and suitable alternative configuration of the lower conductor of Lue, which may be found beneficial in consideration of materials costs and changing market conditions, as well as electrical properties such as insulation protecting against parasitic capacitance, as Lue contemplated other suitable conductors may be used in their device.
Claims 31 and 34 are under 35 U.S.C. 103 as being unpatentable over Lue in view of Lee.
Regarding claim 31, Lue discloses method for forming a semiconductor device structure (a method to for the device of FIGS. 1-2 ¶ [0013-0014]; FIG. 10 also illustrates a circuit diagram where the device of FIGS. 1-2 is implemented ¶ [0024]), comprising: forming a two-dimensional array of semiconductor channels (FIGS. 1-2 and 10, an array of vertical channel structures 150 is formed ¶ [0028]); forming a ferroelectric dielectric layer (FIG. 1, ferroelectric memory material 115 is formed to surround channel region 152 of channel 150 ¶ [0031]) surrounding the semiconductor channels;
forming an electrode material layer (FIG. 1, the portion of word line conductor 110 within the region designated transistor 110T functions as an electrode material layer formed over sidewalls of ferroelectric material 115 ¶ [0029-0031]) over the ferroelectric dielectric layer; forming a metal layer (FIG. 1, the portion of word line conductor 110 outside the region designated transistor 110T functions as a metal layer that surrounds channels 150 ¶ [0029-0031]; Lue discusses using a metal material such as tungsten to form the word lines, which a person of ordinary skill in the art before the effective filing date of the claimed invention would find obvious for providing a conductive word line structure ¶ [0056]) surrounding the semiconductor channels; forming top electrodes (FIG. 1, contact plug 148 is formed on channels 150 ¶ [0029]) on the semiconductor channels; and forming conductive features (FIG. 1, overlying bit lines 147 are formed over contact plugs 148, which serve as bit lines ¶ [0029]) over the top electrodes, wherein the conductive features serve as bit lines.
Lue does not disclose forming a first dielectric material layer over a substrate; forming metal lines in the first dielectric material layer, and forming bottom electrodes over the metal lines; in contrast, Lue uses a configuration wherein a doped well functions in the capacity of a reference conductor (FIG. 1, reference conductor 149 may be n-type doped over p-type doped semiconductor body 100 ¶ [0028]) to provide a source region for the vertical-type GAA transistor structures (FIG. 10, see common source lines CSL of the circuit diagram ¶ [0068]), though Lue does mention that the reference conductor may be any suitable conductive material (¶ [0028]).
However, Lee discloses a method for forming a semiconductor device structure (a method to form the device of FIGS. 1-3 ¶ [0010-0012]), comprising: forming a first dielectric material layer (FIG. 3, source line insulating layer 122 is formed ¶ [0041]) over a substrate (FIG. 3, substrate 110 is formed ¶ [0034]); forming metal lines (FIG. 3, source lines SL, excluding for a portion contacting channels 160, are formed in layer 122 ¶ [0035]) in the first dielectric material layer; forming a two-dimensional array (FIG. 2, memory cell array MCA is formed ¶ [0033-0034]) of semiconductor channels (FIG. 3, channel layers 160 ¶ [0048]) and bottom electrodes (annotated FIG. 3 reproduced below, segments of source lines SL contacting channels 160 function as bottom electrodes in an array) over the metal lines. A person of ordinary skill in the art before the effective filing date of the claimed invention would also recognize the configuration having a metal line formed in a dielectric layer, set on a substrate as demonstrated in Lee to be a known alternative to the doped well conductor of Lue, which may be found beneficial in consideration of materials costs and changing market conditions, as well as electrical properties such as insulation protecting against parasitic capacitance, as Lue contemplated other suitable conductors may be used in their device.
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Lue and Lee both pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lue in view of Lee to substitute the metal line in a dielectric layer configuration of Lee in place of the doped well of Lue, and in so doing include steps of forming a first dielectric material layer over a substrate; forming metal lines in the first dielectric material layer, and forming bottom electrodes over the metal lines, as Lee demonstrated a known and suitable alternative configuration of the lower conductor of Lue, which may be found beneficial in consideration of materials costs and changing market conditions, as well as electrical properties such as insulation protecting against parasitic capacitance, as Lue contemplated other suitable conductors may be used in their device.
Regarding claim 34, Lue in view of Lee discloses the limitations of claim 31 as detailed above, and they further disclose that the semiconductor channels, the bottom electrodes, the top electrodes, the ferroelectric dielectric layer, the electrode material layer, and the metal layer collectively form a vertical-type gate-all-around (GAA) device structure (Lue FIGS. 1-2, the disclosed device is a GAA device ¶ [0014]), and each GAA device structure is a one-transistor (1T) FeRAM device (Lue FIG. 1, the elements forming upper transistor 110T make a 1T FeRAM device ¶ [0031]; it is not stated that the overall device consists solely of one transistor).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 31 above, and further in view of US patent publication US 20210398994 A1 (Young et al hereinafter Young).
Lee discloses the limitations of claim 31 as detailed above but did not further disclose that the substrate is an interconnect-level dielectric material layer in a Back-End-Of-Line (BEOL) structure. However, Young teaches that having a ferroelectric memory cell array formed in a BEOL structure (e.g. FeRAM device 200 in FIG. 16A ¶ [0103]) can improve the size and memory cell density in the device (¶ [0051]).
Lee and Young both pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Young such that the substrate is an interconnect-level dielectric material layer in a Back-End-Of-Line (BEOL) structure, as Young has demonstrated that doing so can improve the size and memory cell density in the device.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 36 above, and further in view of Lue.
Wang discloses the limitations of claim 36 as detailed above but does not further disclose that the first array and the second array of non-volatile memory cells each comprise vertical-type gate-all-around (GAA) FeRAM devices. Wang does suggest that the memory cell arrays may use FeRAM memory but does not further detail a vertical-type GAA structure for the FeRAM memory cells.
However, Lue discloses a memory array structure which includes vertical type GAA FeRAM structures (FIGS. 1-2 illustrate vertical-type GAA FeRAM structures ¶ [0013-0014]), and Lue also teaches that their disclosed FeRAM structures “can operate with low power and high speed, with program and erase operations resistant to over-erase and over-program conditions” and can be implemented in high-density integrated circuits(¶ [0011]).
Wang and Lue both pertain to the field of methods of semiconductor device structures, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Wang in view of Lue such that the first array and the second array of non-volatile memory cells each comprise vertical-type gate-all-around (GAA) FeRAM devices, in order to implement memory structures that can operate with low power and high speed, with program and erase operations resistant to over-erase and over-program conditions in the device of Wang, as taught by Lue.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20250081469 A1, US 20220352379 A1, and US 20220320180 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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