DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: the repeat portion of "a lower power rail electrically connected to lower portions of the plurality of lower via contacts" at the end of the claim that seems to add no further limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 13-16, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US 20220165885 A1).
Regarding claim 1, Liao et al. teaches an integrated circuit device comprising:
a fin-type active structure elongated in a first horizontal direction [¶0014];
a nanosheet stack on an upper surface of the fin-type active structure, the nanosheet stack including a plurality of nanosheets spaced apart from the upper surface of the fin-type active structure at different vertical distances from the upper surface of the fin-type active structure [Fig. 22, ¶0014];
a gate structure (104) on the fin-type active structure [¶0015],
the gate structure including at least one sub-gate surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure [Fig. 1, ¶0015],
the gate structure being between each of the plurality of nanosheets and elongated in a second horizontal direction [¶0040, gate structure lengthwise perpendicular to fins which the nanosheets are placed on],
the second horizontal direction crossing the first horizontal direction [Fig. 1, ¶0040, perpendicular];
a source/drain structure on the fin-type active structure at a position adjacent to the gate structure and the nanosheet stack in the first horizontal direction [¶0015];
a vertical separation layer including a silicide separation layer (108) and a silicon separation layer (92) in contact with the silicide separation layer [Fig. 22, ¶¶0048 and 0064, 92 may be formed of silicon, 108 can be formed of a metal silicide],
the silicide separation layer being between the source/drain structure (112A) and the nanosheet stack (as seen in attached Fig. 22) and between the source/drain structure and the gate structure [Fig. 22, ¶0047],
the silicide separation layer (108) contacting the source/drain structure (112A) [Fig. 22],
the silicon separation layer (92) being between the silicide separation layer (108) and the nanosheet stack (as seen in attached Fig. 22) and between the silicide separation layer (108) and the gate structure (as seen in attached Fig. 22) [Fig. 22]; and
a bottom dielectric isolation (102) under a lower surface of the gate structure [Fig. 23A, ¶0015, wherein the source/drain structure includes a material including metal [¶¶0066 and 0094, 112A includes metal].
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Regarding claim 2, Liao et al. teaches the integrated circuit device of claim 1, further comprising:
a lower via contact (112C) contacting a portion of the bottom dielectric isolation (102) [¶0015, the gate dielectrics along top surfaces, sidewalls, and bottom surfaces and may extend]; and
a lower power rail (144P) electrically connected to a lower portion of the lower via contact [Fig. 22, ¶0094, the power rail is electrically connected to the lower portion of the lower via contact as they are connected through an interconnect structure that has metal], wherein
the source/drain structure (112A) includes a first source/drain structure (112A, as seen in attached Fig. 22) and a second source/drain structure (112A, as seen in attached Fig. 22) with the gate structure and the nanosheet stack therebetween, and
the lower via contact (112C) is connected to a lower end of the first source/drain structure (112A) [Fig. 22].
Regarding claim 3, Liao et al. teaches the integrated circuit device of claim 2, further comprising:
a device isolation film (128) between the lower power rail (144P) and the bottom dielectric isolation (102),
wherein the lower via contact (112C) passes through the device isolation film (128) [Fig. 22, ¶0083].
Regarding claim 4, Liao et al. teaches the integrated circuit device of claim 2, wherein
the bottom dielectric isolation (102) extends from under the gate structure to contact a lower surface of the second source/drain structure [¶0015, the gate dielectrics along top surfaces, sidewalls, and bottom surfaces and may extend to the source/drain structure].
Regarding claim 5, Liao et al. teaches the integrated circuit device of claim 1, further comprising:
a plurality of lower via contacts (112C) passing through portions of the bottom dielectric isolation (128); and
a lower power rail (144P) electrically connected to lower portions of the plurality of lower via contacts [Fig. 22, ¶0094, the power rail is electrically connected to the lower portion of the lower via contact as they are connected through an interconnect structure that has metal, Fig. 1 shows that there would be a plurality in the device], wherein
the source/drain structure comprises a plurality of first source/drain structures (112A, as seen in attached Fig. 22) and a plurality of second source/drain structures (112A, as seen in attached Fig. 22) alternately provided in the first horizontal direction, and
the plurality of lower via contacts (112C) contact lower surfaces of the plurality of first source/drain structures, and
a lower power rail electrically connected to lower portions of the plurality of lower via contacts [Fig. 1, shows that there is a plurality of the structures, Fig. 22, shows the detailed structures].
Regarding claim 6, Liao et al. teaches the integrated circuit device of claim 5, wherein the bottom dielectric isolation (102) extends from under the gate structure to contact a lower surface of a corresponding second source/drain structure among the plurality of second source/drain structures [¶0015, the dielectric isolation extends across the sidewalls and bottom surfaces of nanostructures and fins].
Regarding claim 7, Liao et al. teaches the integrated circuit device of claim 6, further comprising: an upper via contact (112B) contacting an upper surface of the corresponding second source/drain structure (112A, as seen in attached Fig. 22) [as seen in attached Fig. 22, ¶¶0069 and 0070, seen to be in contact in Fig. 22].
Regarding claim 8, Liao at el. teaches the integrated circuit device of claim 5, wherein the gate structure comprises a main gate (104) extending in the second horizontal direction on the nanosheet stack [Fig. 10A, ¶0060].
Regarding claim 13, Liao et al. teaches the integrated circuit device of claim 1, wherein
the silicide separation layer includes one of phosphorus (P), arsenic (As), boron (B), and aluminum (Al) [¶¶0048-0049, boron and phosphorous],
the silicide separation layer (108) includes at least one of titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide, titanium gallide, nickel gallide, cobalt gallide, tantalum gallide, and tungsten gallide [¶0064], and
the silicon separation layer includes at least one of metal silicide, metal germanide, metal gallide, and metal aluminide [¶0049].
Regarding claim 14, Liao et al. teaches the integrated circuit device of claim 1, wherein the source/drain structure (112A) includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd [¶0066].
Regarding claim 15, Liao et al. teaches an integrated circuit device comprising:
a fin-type active structure elongated in a first horizontal direction [¶0014];
a nanosheet stack on an upper surface of the fin-type active structure, the nanosheet stack including a plurality of nanosheets spaced apart from the upper surface of the fin-type active structure at different vertical distances from the upper surface of the fin-type active structure [Fig. 22, ¶0014];
a gate structure (104) on the fin-type active structure [¶0015],
the gate structure (104) including at least one sub-gate surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure [Fig. 1, ¶0015],
the gate structure (104) being between each of the plurality of nanosheets and elongated in a second horizontal direction [¶0040, gate structure lengthwise perpendicular to fins which the nanosheets are placed on],
the second horizontal direction crossing the first horizontal direction [Fig. 1, ¶0040, perpendicular];
a source/drain structure including a first source/drain structure (112A) and a second source/drain structure (112A) on the fin-type active structure respectively at positions adjacent to the gate structure (104), the first source/drain structure and the second source/drain structure facing the nanosheet stack in the first horizontal direction [Fig. 22, face is a broad term and it can be seen in a portion of the source/drain structures face the nanosheet stack in the first horizontal direction as they are seen in the same cut of the circuit device], and the first source/drain structure and the second source/drain structure being among a plurality of first source/drain structures and a plurality of second source/drain structures provided alternately in the first horizontal direction on the fin-type active structure [Fig. 1, ¶0021, Fig. 1 shows there are multiple structures that are shown further in detail in other figures, such as Fig. 22];
a vertical separation layer including a silicide separation layer (108) and a silicon separation layer (92) in contact with the silicide separation layer [Fig. 22, ¶¶0048 and 0064, 92 may be formed of silicon, 108 can be formed of a metal silicide],
the vertical separation layer including a first vertical separation layer between the first source/drain structure and each of the nanosheet stack and the gate structure [Fig. 22],
the vertical separation layer including a second vertical separation layer between the second source/drain structure and each of the nanosheet stack and the gate structure [Fig. 22],
the silicide separation layer (108) of the first vertical separation layer contacting the first source/drain structure (112A) and the silicide separation (108) layer of the second vertical separation layer contacting the second source/drain structure (112A) [Fig. 22],
the silicon separation layer (92) of the first vertical separation layer being between the silicide separation layer (108) of the first vertical separation layer and each of the nanosheet stack and the gate structure [Fig. 22], and
the silicon separation layer (92) of the second vertical separation layer being between the silicide separation layer (108) of the second vertical separation layer and each of the nanosheet stack and the gate structure [Fig. 22]; and
a bottom dielectric isolation (102) in contact with a lower surface of the gate structure (104) [Fig. 23A, ¶0015], wherein
the first source/drain structure and the second source/drain structure of the source/drain structure each include a material including metal [¶0066, 112A may include various metals].
Regarding claim 16, Liao et al. teaches the integrated circuit device of claim 15,
wherein the first source/drain structure (112A) extends through the bottom dielectric isolation (102), and
a lower surface of the second source/drain structure (112A) contacts the bottom dielectric isolation (102) [¶0015, the gate dielectric is along top surfaces, sidewalls, and bottom surfaces and may extend to be in contact with the source and drain structure].
Regarding claim 20, Liao et al. teaches an integrated circuit device comprising:
a fin-type active structure elongated in a first horizontal direction [¶0014];
a nanosheet stack on an upper surface of the fin-type active structure, the nanosheet stack including a plurality of nanosheets spaced apart from the upper surface of the fin-type active structure at different vertical distances from the upper surface of the fin-type active structure [Fig. 22, ¶0014];
a gate structure (104) on the fin-type active structure [¶0015],
the gate structure (104) including at least one sub-gate surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure [Fig. 1, ¶0015],
the gate structure (104) being between each of the plurality of nanosheets and elongated in a second horizontal direction [¶0040, gate structure lengthwise perpendicular to fins which the nanosheets are placed on],
the second horizontal direction crossing the first horizontal direction [Fig. 1, ¶0040, perpendicular];
a source/drain structure including a first source/drain structure (112A) and a second source/drain structure (112A) on the fin-type active structure respectively at positions adjacent to the gate structure (104), the first source/drain structure and the second source/drain structure facing the nanosheet stack in the first horizontal direction [Fig. 22, face is a broad term and it can be seen in a portion of the source/drain structures face the nanosheet stack in the first horizontal direction as they are seen in the same cut of the circuit device], and the first source/drain structure and the second source/drain structure being among a plurality of first source/drain structures and a plurality of second source/drain structures provided alternately in the first horizontal direction on the fin-type active structure [Fig. 1, ¶0021, Fig. 1 shows there are multiple structures that are shown further in detail in other figures, such as Fig. 22];
a vertical separation layer including a silicide separation layer (108) and a silicon separation layer (92) in contact with the silicide separation layer [Fig. 22, ¶¶0048 and 0064, 92 may be formed of silicon, 108 can be formed of a metal silicide],
the vertical separation layer including a first vertical separation layer between the first source/drain structure and each of the nanosheet stack and the gate structure [Fig. 22],
the vertical separation layer including a second vertical separation layer between the second source/drain structure and each of the nanosheet stack and the gate structure [Fig. 22, shows two and one can be seen as the first and the other, the second],
the silicide separation layer (108) of the first vertical separation layer contacting the first source/drain structure (112A) and the silicide separation (108) layer of the second vertical separation layer contacting the second source/drain structure (112A) [Fig. 22],
the silicon separation layer (92) of the first vertical separation layer being between the silicide separation layer (108) of the first vertical separation layer and each of the nanosheet stack and the gate structure [Fig. 22], and
the silicon separation layer (92) of the second vertical separation layer being between the silicide separation layer (108) of the second vertical separation layer and each of the nanosheet stack and the gate structure [Fig. 22];
a bottom dielectric isolation (102) in contact with a lower surface of the gate structure (104) [Fig. 23A, ¶0015];
a lower via contact (112C) passing through at a portion of the bottom dielectric isolation (102), the lower via contact contacting a lower surface of the first source/drain structure (112A) [¶0015, the bottom dielectric isolation can be seen to extend on sidewalls and with that extension, the lower via contact be thought to pass through that portion to reach the lower surface of the first source/drain structure];
a lower power rail (144P) electrically connected to a lower portion of the lower via contact [Fig. 22, ¶0094, the power rail is electrically connected to the lower portion of the lower via contact as they are connected through an interconnect structure that has metal; and
an upper via contact (112B) contacting an upper surface of the second source/drain structure (112A, as seen in attached Fig. 22) [as seen in attached Fig. 22, ¶¶0069 and 0070, seen to be in contact in Fig. 22], wherein
the bottom dielectric isolation (102) extends from under the gate structure to contact a lower surface of the second source/drain structure [¶0015, the gate dielectrics along top surfaces, sidewalls, and bottom surfaces and may extend to the source/drain structure], and
the first source/drain structure (112A) and the second source/drain structure (112A) of the source/drain structure includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd [¶0066].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 20220165885 A1) in view of Lin et al. (US 20210336012 A1).
Regarding claim 9, Liao et al. teaches the integrated circuit device of claim 5
Liao et al. doesn’t teach a capping insulating pattern on the gate structure and on at least one sub-gate and the nanosheet stack.
Lin et al. teaches a capping insulating pattern (self-aligned capping) on the gate structure [Fig. 14, ¶0035], wherein
the capping insulating pattern is on the at least one sub-gate and the nanosheet stack [Fig. 14, ¶0035, the self-aligned capping is on the gate structures and Fig. 14 shows the capping is on a nanosheet stack and sub-gate].
It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the integrated circuit device as taught by Liao et al. with the capping insulating pattern as taught by Lin et al. because the capping insulating pattern is used to protect the area from other etching processes that are used to create the integrated circuit device [Lin et al., ¶0035].
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 20220165885 A1) in view of Lin et al. (US 20210336012 A1) and Chang et al. (US 20230026310 A1).
Regarding claim 10, Liao et al. in view of Lin et al. teaches the integrated circuit device of claim 9, further comprising:
the vertical separation layer (108) extends between the nanosheet stack and an adjacent one of the plurality of first source/drain structures [Liao et al., Fig. 22],
the vertical separation layer (108) extends between the nanosheet stack and an adjacent one of the plurality of second source/drain structures [Liao et al., Fig. 22],
the vertical separation layer (108) extends between the gate structure and the adjacent one of the plurality of first source/drain structures [Liao et al., Fig. 22],
the vertical separation layer (108) extends between the gate structure and the adjacent one of the plurality of second source/drain structures [Liao et al., Fig. 22],
the vertical separation layer (108) is between lower insulating layer and the plurality of first source/drain structures [Liao et al., Fig. 22], and
the vertical separation layer (108) is between lower insulating layer and the plurality of second source/drain structures [Liao et al., Fig. 22].
Liao et al. in view of Lin et al. doesn’t teach a lower insulating layer.
Chang et al. a lower insulating layer (182) in contact with a lower surface of the bottom dielectric isolation (186) between the plurality of first source/drain structures (154) and the plurality of second source/drain structures (156) [Fig. 2V-1], wherein
a vertical level of a lower surface of the lower insulating layer (182) is the same as a vertical level of the lower surfaces of the plurality of first source/drain structures (154) and lower surfaces of the plurality of second source/drain structures (156),
It would have been obvious for a person of ordinary skill in the art to combine the integrated circuit device as taught by Liao et al. in view of Lin et al. and the lower insulating layer as taught by Chang et al. because it would ensure there is less leakage in the device.
Regarding claim 11, Liao et al. in view of Lin et al. and Chang et al. teaches the integrated circuit device of claim 10, wherein
a vertical level of a lower surface of the vertical separation layer (108, Liao et al.) is the same as the vertical level of the lower surfaces of the plurality of first source/drain structures (112A, Liao et al.) and the lower surfaces of the plurality of second source/drain structures (112A, Liao et al.) [Liao et al., Fig. 22, lower surfaces is ambiguous and it can be said that the lower surface of the vertical separation layer is at the same vertical level of the lower surface of the source/drain structures], and
a vertical level of an upper surface of the vertical separation layer (138, Chang et al.) is higher than a vertical level of an upper surface of the nanosheet stack (112, Chang et al.) [Fig. 2K-1, 138 is a gate spacer layer is formed to separate the source/drain features from the gate structure ¶0051 and is seen to extend above the nanostructure].
Regarding claim 12, Liao et al. in view of Lin et al. and Chang et al. teaches the integrated circuit device of claim 11, wherein
a first contact surface (Liao et al., as seen in attached Fig. 22) is where the upper via contacts the upper surface of the corresponding second source/drain structure,
a second contact surface (Liao et al., as seen in attached Fig. 22) where one of the plurality of lower vias contacts the lower surface of one of the plurality of the first source/drain structures,
a difference between a vertical level of the first contact surface and a vertical level of the second contact surface is equal to vertical lengths of the plurality of first source/drain structures and equal to vertical lengths of the plurality of second source/drain structures [Liao et al., as seen in attached Fig. 22, ¶0067, 112A has the same heights].
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 20220165885 A1) in view of Chang et al. (US 20230026310 A1).
Regarding claim 17, Liao et al. teaches the integrated circuit device of claim 16, further comprising:
a lower via contact (112C) contacting a lower surface of the first source/drain structure (112A);
a lower power rail (144P) electrically connected to a lower portion of the lower via contact (112C); and
an upper via (112B) contact contacting an upper surface of the second source/drain structure (112A).
Liao et al. doesn’t teach a lower insulating layer.
Chang et al. teaches a lower insulating layer (182) in contact with a lower surface of the bottom dielectric isolation (186);
the first source/drain (156) structure extends through the lower insulating layer (182), and
the second source/drain structure (154) is above the lower insulating layer and spaced apart from the lower insulating layer [Fig. 2V-1, ¶0136].
It would have been obvious for a person of ordinary skill in the art to combine the integrated circuit device as taught by Liao et al. and the lower insulating layer as taught by Chang et al. because it would ensure there is less leakage in the device.
Regarding claim 18, Liao et al. in view of Chang et al. teaches the integrated circuit device of claim 17, wherein
the silicide separation layer includes at least one of phosphorus (P), arsenic (As), boron (B), and aluminum (Al) [Liao et al., ¶¶0048-0049, boron and phosphorous],
the silicide separation layer (108) includes at least one of titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide, titanium gallide, nickel gallide, cobalt gallide, tantalum gallide, and tungsten gallide [Liao et al., ¶0064],
the silicon separation layer is includes at least one of metal silicide, metal germanide, metal gallide, and metal aluminide [Liao et al., ¶0049],
the first vertical separation layer (150) is between the first source/drain structure and each of the at least one sub-gate (170), the lower insulating layer (182), and the bottom dielectric isolation (186) [Chang et al., Fig. 2V-1, ¶0158, lateral separation], and
the second vertical separation layer (150) is between second source/drain structure (156) and each of the at least one sub-gate (170), and the lower insulating layer (182) [Chang et al., Fig. 2V-1, ¶0158, lateral separation].
Regarding claim 19, Liao et al. in view of Chang et al. teaches the integrated circuit device of claim 18, wherein
a vertical level of an upper surface of the first vertical separation layer (108) is level with a vertical level of an upper surface of the second vertical separation layer (108) [Liao et al., Fig. 22], and
a vertical level of a lower surface of the first vertical separation layer is lower than a vertical level of a lower surface of the second vertical separation layer [Liao et al., Fig. 22, ¶0112, in some embodiments 138 and 108 may be merged together which would allow for the lower surface of the first to be lower than the lower surface of the second vertical separation layer].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
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/NOOR MOHAMMAD ISMAIL TAHIR/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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