CTNF 18/435,178 CTNF 97482 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: Display Device that Includes Color Filters that Overlap Each Other in the Peripheral Region . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 5, 7-8, 10-11, and 16 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Joo et al (US 2020/0365833) . Regarding Claim 1, Joo et al discloses a display device (display panel DP [0048] Fig 4A) comprising: a first display substrate (lower substrate 100 [0045] Fig 3B) including a first base layer (first base substrate BS1 [0060] Fig 4A) comprising a display region (display region DA [0055] Fig 1A) and a non-display region (non-display region NDA [0053] Fig 1A) adjacent to the display region (DA Fig 1A); a second display substrate (upper display substrate 200 [0045] Fig 3B) including a second base layer (second base substrate BS2 [0090] Fig 4A) comprising pixel regions (Pxa-B, Pxa-G, and Pxa-R [0056] Fig 4A) overlapped with the display region (DA Fig 2) and a peripheral region (peripheral region NPxa [0056] Fig 4A) adjacent to the pixel regions (Pxa-B, Pxa-G, and Pxa-R Fig 4A), and color filters (color filter parts CF-B, CF-G, and CF-R [0125] Fig 4A) disposed on the second base layer (BS2 Fig 4A), and spaced apart from the first display substrate (BS1 Fig 4A); and a sealing member (sealant SLM [0046] Fig 1B) interposed between the first display substrate (100 Fig 1B) and the second display substrate (200 Fig 1B) and overlapped with the non-display region (NDA Fig 1A), wherein the first display substrate (100 Fig 3B) comprises: light emitting elements (display element layer DP-LED [0090] Fig 3B and Fig 4A) overlapped with the pixel regions (Pxa-B, Pxa-G, and Pxa-R Fig 4A), respectively; an encapsulation layer (encapsulation member TFE [0080] Fig 3B and Fig 4A) to cover the light emitting elements (DP-LED Fig 3B and Fig 4A); a split pattern (light shield pattern BP [0083] and separation wall pattern WP [0123] Fig 4A) including openings (shown in annotated Fig 4A) overlapped with the pixel regions (Pxa-B, Pxa-G, and Pxa-R Fig 4A), respectively, and disposed on the encapsulation layer (TFE Fig 3B and Fig 4A); and light control patterns (light control parts CCP1, CCP2, and CCP3 [0099] Fig 4A) disposed in the openings (shown in annotated Fig 4A), and wherein an end portion of an organic layer (TFE may include organic films [0080] Fig 3B and Fig 4A) of the encapsulation layer (TFE Fig 3B and Fig 4A) overlapped (shown in the combination of Fig 1A, Fig 1B, Fig 3B, and Fig 4A) with the non-display region (NDA Fig 1A and Fig 1B) is covered by the split pattern (BP and WP Fig 4A). PNG media_image1.png 766 924 media_image1.png Greyscale Regarding Claim 5, Joo et al discloses the limitations of claim 1 as explained above. Joo et al further discloses wherein the split pattern (light shield pattern BP [0083] and separation wall pattern WP [0123] Fig 4A) further comprises: a first part (WP in the peripheral region NPxa Fig 4A) disposed in the display region (DA Fig 1B) and a second part (WP in the non-display region NDA shown in the combination of Fig 4A and Fig 1B/since there are no pixels PX in the NDA region as shown in Fig 1A) and disposed in the non-display region (NDA Fig 1B) and extending from the first part, and wherein the sealing member (SLM Fig 1B) is interposed between the second part (WP in the non-display region NDA Fig 1B) and the second display substrate (200 Fig 1B). Regarding Claim 7, Joo et al discloses the limitations of claim 1 as explained above. Joo et al further discloses wherein the first display substrate (100 Fig 3B) further comprises: dam patterns (pixel defining film PDL [0065] Fig 4A) disposed on the first base layer (BS1 Fig 4A) and overlapped (shown in the combination of Fig 1B, Fig 3B, and Fig 4A) with the non-display region (NDA Fig 1B), wherein a boundary of the organic layer (organic film OL [0094] Fig 4A) is defined by a first one of the dam patterns (PDL Fig 4A) and a boundary of the split pattern (BP and WP Fig 4A) is defined by a second other one of the dam patterns (PDL Fig 4A), and wherein the second dam pattern (outer PDL Fig 4A) is more closer to the sealing member (SLM Fig 1B) than the first dam pattern (inner PDL Fig 4A). Regarding Claim 8, Joo et al discloses the limitations of claim 7 as explained above. Joo et al further discloses wherein each of the dam patterns (PDL Fig 4A) has a closed-line shape to surround the display region (DA Fig 1B). Regarding Claim 10, Joo et al discloses the limitations of claim 1 as explained above. Joo et al further discloses wherein the first display substrate (100 Fig 3B and Fig 4A) and the second display substrate (200 Fig 3B and Fig 4A) are spaced apart from each other while interposing a cell gap (area where the filling layer BFL [0045] is located Fig 4A) between the first display substrate (100 Fig 3B and Fig 4A) and the second display substrate (200 Fig 3B and Fig 4A). Regarding Claim 11, Joo et al discloses the limitations of claim 10 as explained above. Joo et al further discloses further comprising: a filling material (BFL Fig 4A) including an organic material (organic binder [0132] Fig 4A) that fills the cell gap (area where the filling layer BFL is located Fig 4A). Regarding Claim 16, Joo et al discloses the limitations of claim 1 as explained above. Joo et al further discloses wherein the first display substrate (100 Fig 3B) further comprises: an upper cover layer (inorganic binder of the filling layer BFL 0131] Fig 4A) configured to cover the split pattern (BP and WP Fig 4A) and the light control patterns (light control parts CCP1, CCP2, and CCP3 [0099] Fig 4A), and including an inorganic material (inorganic [0132]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US 2020/0365833) in view of Jang et al (US 2021/0384457), and in further view of Lee et al (US 2014/0175972) . Regarding Claim 2, Joo et al discloses the limitations of claim 1 as explained above. Joo et al does not disclose wherein the second display substrate further comprises: a lower refractive layer to cover the color filters; an upper cover layer to cover the lower refractive layer; and a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region, and wherein the sealing member contacts the step difference compensating layer and the first display substrate. Jang et al, in the related art of semiconductor devices that include display devices, discloses wherein the second display substrate (second substrate SUB2 [0098], black matrix BM [0098], color filters CF1, CF2, CF3 [0095], low refraction layer LRL [0095], and first insulation layer IL1 [0095] Fug 5) further comprises: a lower refractive layer (LRL Fig 5) to cover the color filters (CF1, CF2, CF3 Fig 5); and an upper cover layer (IL1 Fig 5) to cover the lower refractive layer (LRL Fig 5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Joo et al to include a lower refractive layer and an upper cover layer, and color filters at different steps as taught by Jang et al in order to further control the scattering particles to be emitted [0109]. Further, a person of ordinary skill in the art would have recognized that having an insulating layer on the lower refractive layer would be advantageous in protecting the device from unwanted electrical effects and overheating (see MPEP 2143.I(D)). The combination oof Joo et al and Jang et al does not disclose a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region, and wherein the sealing member contacts the step difference compensating layer and the first display substrate. Lee et al, in the related art of semiconductor devices that include display devices, discloses a step difference compensating layer (step-difference compensation portion 140a [0032] Fig 2B and Fig 3A) that is overlapped with the non-display region (non-display region [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al and Jang et al to include a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region as taught by Lee et al in order to compensate for a step difference between the display region and the non- display region [0048] which would improve the encapsulation reliability of the TFE. Further, a person of ordinary skill in the art would have recognized that controlling the flow of encapsulation materials from entering the display area would prevent water and oxygen intrusion which may hinder the optical functioning of the device (see MPEP 2143.I(D)). The combination of Joo et al, Jang et al, and Lee et al now discloses a step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) that covers the upper cover layer and is overlapped with the non-display region (non-display region Fig 3A Lee et al/non-display region NDA Fig 1A Joo et al), wherein the sealing member (sealant SLM [0046] Fig 1B Joo et al) contacts the step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) and the first display substrate (100 Fig 3B Joo et al). Regarding Claim 3, Joo et al discloses the limitations of claim 1 as explained above. Joo et al does not disclose wherein the second display substrate further comprises: an upper cover layer to cover the color filters; and a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region, and wherein the sealing member contacts the step difference compensating layer and the first display substrate. Jang et al, in the related art of semiconductor devices that include display devices, discloses wherein the second display substrate (second substrate SUB2 [0098], black matrix BM [0098], color filters CF1, CF2, CF3 [0095], low refraction layer LRL [0095], and first insulation layer IL1 [0095] Fug 5) further comprises: an upper cover layer (IL1 Fig 5) to cover the color filters (color filters CF1, CF2, CF3 [0095] Fig 5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Joo et al to include an upper cover layer, and color filters at different steps as taught by Jang et al in order to further control the scattering particles to be emitted [0109]. Further, a person of ordinary skill in the art would have recognized that having an insulating layer on the color filter layer would be advantageous in protecting the device from unwanted electrical effects and overheating (see MPEP 2143.I(D)). The combination oof Joo et al and Jang et al does not disclose a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region, and wherein the sealing member contacts the step difference compensating layer and the first display substrate. Lee et al, in the related art of semiconductor devices that include display devices, discloses a step difference compensating layer (step-difference compensation portion 140a [0032] Fig 2B and Fig 3A) that is overlapped with the non-display region (non-display region [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al and Jang et al to include a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region as taught by Lee et al in order to compensate for a step difference between the display region and the non-display region [0048] which would improve the encapsulation reliability of the TFE. Further, a person of ordinary skill in the art would have recognized that controlling the flow of encapsulation materials from entering the display area would prevent water and oxygen intrusion which may hinder the optical functioning of the device (see MPEP 2143.I(D)). The combination of Joo et al, Jang et al, and Lee et al now discloses a step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) that covers the upper cover layer and is overlapped with the non-display region (non-display region Fig 3A Lee et al/non-display region NDA Fig 1A Joo et al), wherein the sealing member (sealant SLM [0046] Fig 1B Joo et al) contacts the step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) and the first display substrate (100 Fig 3B Joo et al) . 07-21-aia AIA Claim s 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US 2020/0365833) in view of Kim et al (US 2021/0028236) . Regarding Claim 4, Joo et al discloses the limitations of claim 1 as explained above. Joo et al does not disclose wherein the first display substrate further comprises: a dummy pattern disposed in the non-display region, wherein a material of the dummy pattern is the same as a material of one of the light control patterns, and wherein the sealing member is interposed between the dummy pattern and the second display substrate. Kim et al, in the related art of semiconductor devices that include wherein the first display substrate (lower substrate 100 [0045] Fig 3B) further comprises: a dummy pattern (dummy element 148 [0072] Fig 6A) disposed in the non-display region (non-display area NDA [0056] Fig 6A), wherein a material of the dummy pattern (dummy element 148 [0072] Fig 6A) is the same as a material (may be the same material as 146 [0092] Fig 6A) of one of the light control patterns (third element 146 [0077] Fig 6A). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Joo et al to include forming a dummy pattern on the first base layer overlapped with the non-display region, wherein the third light control pattern and the dummy pattern include the same material as taught by Kim et al in order to reduce or prevent deterioration of each element of the color conversion layer and possibly minimize or reduce stains due to the elements in the display area [0095]. Further, a person of ordinary skill in the art would have recognized that reducing the deterioration of each element would improve the reliability problems due to deterioration [0096] (see MPEP 2143.I(D)). The combination of Joo et al and Kim et al now discloses wherein the sealing member (sealant SLM [0046] Fig 1B Joo et al) is interposed between the dummy pattern (148 Fig 6A) and the second display substrate (200 Fig 1B Joo et al). Regarding Claim 17, Joo et al discloses a method (method [0082]) for manufacturing a display device (display panel DP [0048] Fig 4A), the method comprising: forming a working substrate (lower substrate 100 [0045] Fig 3B) including a first base layer (first base substrate BS1 [0060] Fig 4A) including a display region (display region DA [0055] Fig 1A) and a non-display region (non-display region NDA [0053] Fig 1A), a circuit layer (circuit element layer DP-CL [0060] Fig 3B) disposed on the first base layer (BS1 Fig 4A) and having a transistor (driver transistor [0059]), a display element layer (display element layer DP-LED [0060] Fig 3B) including a light emitting element (light emitting element LED [0059]) disposed on the circuit layer (DP-CL Fig 3B) and connected to the transistor (driving transistor [0059]), and an encapsulation layer (encapsulation member TFE [0080] Fig 3B and Fig 4A) to cover the display element layer (DP-LED Fig 3B); forming a split pattern (light shield pattern BP [0083] and separation wall pattern WP [0123] Fig 4A) overlapped with the display region (DA Fig 1A) on the working substrate (100 Fig 3B) to include a first opening (shown in annotated Fig 4A), a second opening (shown in annotated Fig 4A), and a third opening (shown in annotated Fig 4A); forming a first light control pattern (light control part CCP1 [0099] Fig 4A) in the first opening (shown in annotated Fig 4A); forming a second light control pattern light control part CCP2 Fig 4A) in the second opening (shown in annotated Fig 4A); forming a third light control pattern (light control part CCP3 Fig 4A) in the third opening (shown in annotated Fig 4A). PNG media_image2.png 739 892 media_image2.png Greyscale Joo et al does not disclose forming a dummy pattern on the first base layer overlapped with the non-display region, wherein the third light control pattern and the dummy pattern include the same material. Kim et al, in the related art of semiconductor devices that include display devices, discloses forming a dummy pattern (dummy element 148 [0072] Fig 6A) on the first base layer (lower substrate 410 [0139] Fig 6A) overlapped with the non-display region (non-display area NDA [0056] Fig 6A), wherein the third light control pattern (third element 146 [0077] Fig 6A) and the dummy pattern (148 Fig 6A) include the same material (may be the same material as 146 [0092] Fig 6A). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Joo et al to include forming a dummy pattern on the first base layer overlapped with the non-display region, wherein the third light control pattern and the dummy pattern include the same material as taught by Kim et al in order to reduce or prevent deterioration of each element of the color conversion layer and possibly minimize or reduce stains due to the elements in the display area [0095]. Further, a person of ordinary skill in the art would have recognized that reducing the deterioration of each element would improve the reliability problems due to deterioration [0096] (see MPEP 2143.I(D)) . 07-21-aia AIA Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US 2020/0365833) in view of Kim et al (US 2021/0028236), and in further view of Mizushima et al (US 2008/0112047), Jang et al (US 2021/0384457), and Lee et al (US 2014/0175972) . Regarding Claim 18, the combination of Joo et al and Kim et al discloses the limitations of claim 17 as explained above. The combination of Joo et al and Kim et al further discloses further comprising: forming a first display substrate (100 Fig 3B Joo et al) by forming a lower cover layer to cover the split pattern (BP and WP Fig 4A Joo et al), the first control pattern (CCP1 Fig 4A Joo et al), the second control pattern (CCP2 Fig 4A Joo et al), the third control pattern (CCP3 Fig 4A Joo et al), and the dummy pattern (dummy element 148 [0072] Fig 6A Kim et al). The combination of Joo et al and Kim et al does not disclose laminating, with the first display substrate, a second display substrate including a second base layer, color filters disposed on a bottom surface of the second base layer, a lower refractive layer to cover the color filters, an upper cover layer to cover the lower refractive layer, and a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region. Mizushima et al, in the related art of semiconductor devices that include display devices, discloses laminating (optical layer laminated [0077]) which is carried out sequentially in the manufacturing process of a liquid crystal display etc [0077]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al and Kim et al to include laminating, with the first display substrate, a second display substrate including a second base layer, color filters disposed on a bottom surface of the second base layer as taught by Mizushima et al in order to raise the manufacturing process ability of the display device [0077]. Further, a person of ordinary skill in the art would have recognized that having a greater manufacturing process ability would be advantageous in optimizing efficiency and cost effectiveness (see MPEP 2143.I(D)). The combination of Joo et al, Kim et al, and Mizushima et al does not disclose a lower refractive layer to cover the color filters, an upper cover layer to cover the lower refractive layer, and a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region. Jang et al, in the related art of semiconductor devices that include display devices, discloses a lower refractive layer (low refraction layer LRL [0095] Fig 5) to cover the color filters (CF1, CF2, CF3 Fig 5); and an upper cover layer (first insulating layer IL1 [0095] Fig 5) to cover the lower refractive layer (LRL Fig 5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al, Kim et al, and Mizushima et al to include laminating a lower refractive layer and an upper cover layer, and color filters at different steps as taught by Jang et al in order to further control the scattering particles to be emitted [0109]. Further, a person of ordinary skill in the art would have recognized that having an insulating layer on the lower refractive layer would be advantageous in protecting the device from unwanted electrical effects and overheating (see MPEP 2143.I(D)). The combination oof Joo et al, Kim et al, Mizushima et al, and Jang et al does not disclose a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region. Lee et al, in the related art of semiconductor devices that include display devices, discloses a step difference compensating layer (step-difference compensation portion 140a [0032] Fig 2B and Fig 3A) that is overlapped with the non-display region (non-display region [0032]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al, Kim et al, Mizushima et al, and Jang et al to include laminating a step difference compensating layer that covers the upper cover layer and is overlapped with the non-display region as taught by Lee et al in order to compensate for a step difference between the display region and the non-display region [0048] which would improve the encapsulation reliability of the TFE. Further, a person of ordinary skill in the art would have recognized that controlling the flow of encapsulation materials from entering the display area would prevent water and oxygen intrusion which may hinder the optical functioning of the device (see MPEP 2143.I(D)). The combination of Joo et al, Kim et al, Mizushima et al, Jang et al, and Lee et al now discloses a step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) that covers the upper cover layer (IL1 Fig 5 Jang et al) and is overlapped with the non-display region (non-display region Fig 3A Lee et al/non-display region NDA Fig 1A Joo et al) . 07-21-aia AIA Claim s 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Joo et al (US 2020/0365833) in view of Kim et al (US 2021/0028236), Mizushima et al (US 2008/0112047), Jang et al (US 2021/0384457), and Lee et al (US 2014/0175972), and in further view of Wang et al (US 2016/0279917) . Regarding Claim 19, the combination of Joo et al, Kim et al, Mizushima et al, Jang et al, and Lee et al discloses the limitations of claim 18 as explained above. The combination of Joo et al, Kim et al, Mizushima et al, Jang et al, and Lee et al does further discloses wherein the first display substrate (100 Fig 3B and Fig 4A Joo et al) and the second display substrate (200 Fig 3B and Fig 4A Joo et al) are combined with each other while interposing a cell gap (area where the filling layer BFL [0045] is located Fig 4A Joo et al) between the first display substrate (100 Fig 3B and Fig 4A Joo et al) and the second display substrate (200 Fig 3B and Fig 4A Joo et al). The combination of Joo et al, Kim et al, Mizushima et al, Jang et al, and Lee et al does not disclose wherein the first display substrate and the second display substrate are combined with each other through a sealing member in a vacuum-lamination process. Wang et al, in the related art of semiconductor devices that include light emitting devices, discloses a vacuum laminating process for making a liquid crystal device [0017]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Joo et al, Kim et al, Mizushima et al, Jang et al, and Lee et al to include a vacuum-lamination process to combine the first display substrate and second display substrate through a sealing member as taught by Wang et al in order to improve a yield rate of the laminating process by reducing air bubbles and not requiring a de-bubbling process [0017]. Further, a person of ordinary skill in the art would have recognized that improving the yield rate would optimize the efficiency and cost effectiveness of the manufacturing process (see MPEP 2143.I(D)). Regarding Claim 20, the combination of Joo et al, Kim et al, Mizushima et al, Jang et al, Lee et al, and Wang et al discloses the limitations of claim 19 as explained above. The combination of Joo et al, Kim et al, Mizushima et al, Jang et al, Lee et al, and Wang et al further discloses wherein the sealing member (SLM Fig 1B Joo et al) is interposed between the step difference compensating layer (140a Fig 2B and Fig 3A Lee et al) and the dummy pattern (148 Fig 6A Kim et al) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 6, 9, and 12-15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 6 : Regarding Claim 6, Joo et al discloses the limitations of claim 5 as explained above. Wu (US 2017/0052406) discloses wherein the second part (black matrix 101 [0021] in the non-display region 11 [0022] Fig 4) comprises: at least one pattern hole (via hole 104 [0021]) formed on the split pattern (101). The reason for the indication of allowability of Claim 6 is the inclusion of at least one pattern hole formed through the split pattern while extending from a top surface of the split pattern and a bottom surface of the split pattern, and wherein the sealing member is disposed inside the at least one pattern hole. Specifically , the prior art reference Joo et al does not disclose a pattern ole through the split pattern and wherein the sealing member is disposed inside the at least on pattern hole as claimed. Further, should another prior art reference be found that disclose this feature, it would not be obvious to a person of ordinary skill in the art to make the alteration to the reference Joo et al. It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art. Claim 9: Regarding Claim 9, Joo et al discloses the limitations of claim 7 as explained above. Joo et al further discloses wherein the organic layer (OL Fig 4A) is disposed between a first inorganic layer (inorganic film IL [0094] Fig 4A) of the encapsulation layer (TFE Fig 4A). The reason for the indication of allowability of Claim 9 is the inclusion of a second inorganic layer of the encapsulation layer, the first inorganic layer and the second inorganic layer contact each other in the non-display region and cover at least one of the dam patterns. Specifically , the prior art reference Joo et al does not disclose a second inorganic layer of the encapsulation layer in the manner required by the claim limitations. Further, should a prior art reference be found that discloses the second inorganic layer and the first inorganic layer contact each other and cover at least one of the dam patterns, it would not be obvious to a person of ordinary skill in the art to make this alteration to Joo et al because it would require the first inorganic layer to be laminated first, followed by the organic layer, then followed by the second inorganic layer. It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art. Claim 12: Regarding Claim 12, Joo et al discloses the limitations of claim 1 as explained above. Joo et al further discloses wherein the color filters comprise: a first color filter, a second color filter, and a third color filter. The reason for the indication of allowability of Claim 12 is the inclusion of wherein at least two color filters of the first color filter, the second color filter, and the third color filter are overlapped with each other in the peripheral region. Specifically , the prior art reference Joo et al does not disclose color filters overlapped with each other in the peripheral region as in the instant application. Further, should another prior art reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to make this alteration to the reference Joo et al. It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art. Claim 13 would be allowable based on its dependency on Claim 12 . Claim 14 would be allowable based on its dependency on Claim 13 . 13-03 Claim 15 would be allowable based on its dependency on Claim 14. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Related Cited Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ann et al (US 11158682) which discloses a filter layer that surrounds the display area on the plane [column 1, lines 30-67], and Wu et al (US 2017/0052406) which discloses a black matrix and a via hole [0026] . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.P.S./Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/435,178 Page 2 Art Unit: 2812 Application/Control Number: 18/435,178 Page 3 Art Unit: 2812 Application/Control Number: 18/435,178 Page 4 Art Unit: 2812 Application/Control Number: 18/435,178 Page 5 Art Unit: 2812 Application/Control Number: 18/435,178 Page 6 Art Unit: 2812 Application/Control Number: 18/435,178 Page 7 Art Unit: 2812 Application/Control Number: 18/435,178 Page 8 Art Unit: 2812 Application/Control Number: 18/435,178 Page 9 Art Unit: 2812 Application/Control Number: 18/435,178 Page 10 Art Unit: 2812 Application/Control Number: 18/435,178 Page 11 Art Unit: 2812 Application/Control Number: 18/435,178 Page 12 Art Unit: 2812 Application/Control Number: 18/435,178 Page 13 Art Unit: 2812 Application/Control Number: 18/435,178 Page 14 Art Unit: 2812 Application/Control Number: 18/435,178 Page 15 Art Unit: 2812 Application/Control Number: 18/435,178 Page 16 Art Unit: 2812 Application/Control Number: 18/435,178 Page 17 Art Unit: 2812 Application/Control Number: 18/435,178 Page 18 Art Unit: 2812 Application/Control Number: 18/435,178 Page 19 Art Unit: 2812 Application/Control Number: 18/435,178 Page 20 Art Unit: 2812
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