DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 Modification A in the reply filed on 19 May 2026 is acknowledged. Claims 1-20 are pending in the application, with claims 3, 14-16, and 18-19 presently withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6-10, 12, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li-Wei Feng et al. (US 20230309291 A1; hereinafter Feng).
PNG
media_image1.png
611
850
media_image1.png
Greyscale
Regarding Claim 1, Feng discloses a semiconductor device (Fig. 1, Fig. 4, Fig. 9) comprising:
an active region (12; ¶0013) defined by an element isolation film (14; ¶0013) in a substrate (10; ¶0013);
a word line (WL; ¶0015) extending in a first horizontal direction (D2) in the substrate (10);
a bit line (204 of BL; ¶0017) extending in a second horizontal direction (D3) crossing the first horizontal direction on the substrate (Fig. 4 and Fig. 9);
an additional pad (S1; ¶0023) disposed on the active region (12); and
a buried contact (M1; ¶0023) on the additional pad (S1)
wherein the buried contact (M1) is electrically connected to the active region (12) by the additional pad (S1) (¶0023),
wherein the additional pad (S1) comprises a first surface (Annotated Fig. 9; surf1) that overlaps the word line (WL) in a vertical direction (up/down in Fig. 9), and a second surface (Annotated Fig. 9; surf2) that is free of overlap with the word line (WL) in the vertical direction, and
wherein, the first surface (surf1) meets the second surface (surf2) at a cusp (Annotated Fig. 9; cusp).
Regarding Claim 2, Feng discloses the semiconductor device of claim 1, wherein the additional pad (S1) comprises a polysilicon layer (¶0023).
Regarding Claim 6, Feng discloses the semiconductor device of claim 1, wherein the active region (12) comprises a first impurity region (12a1) and second impurity regions (12a2) (¶0014-¶0015) spaced apart from each other with the first impurity region (12a1) therebetween (Fig. 9), wherein the semiconductor device further comprises a direct contact (202; ¶0017) electrically connecting the bit line (204 of BL) to the first impurity region (12a1) (Fig. 9 and ¶0017), and wherein the buried contact (M1) is electrically connected to the second impurity region (12a2) by the additional pad (S1) (Fig. 9 and ¶0023).
Regarding Claim 7, Feng discloses a semiconductor device (Fig. 1, Fig. 4, and Fig. 9) comprising:
a substrate (10; ¶0013);
a plurality of active regions (12; ¶0013) extending in an oblique direction (D1) in the substrate (10);
a plurality of word lines (WL; ¶0015) crossing the plurality of active regions (12) in a first horizontal direction (D2) and separating each of the plurality of active regions (12) into a first impurity region (12a1) and a second impurity region (12a2) (¶0014-¶0015);
a plurality of bit lines (204 of BL; ¶0017) extending in a second horizontal direction (D3) crossing the first horizontal direction (D2) on the substrate (10);
a plurality of direct contacts (202; ¶0017) electrically connecting the plurality of bit lines (204 of BL) to the first impurity regions (12a1) (Fig. 9), respectively;
a first trench (SC; ¶0019) extending in the first horizontal direction and exposing the second impurity regions (12a2) of two adjacent active regions (12) among the plurality of active regions (as described in ¶0019);
a second trench (R1; ¶0020) passing through a lower surface of the first trench (SC) in the first trench (as shown in Fig. 8);
a plurality of additional pads (S1; ¶0023) between the first trench and the second trench (S1 exists to fill and be between SC and R1); and
a plurality of buried contacts (M1; ¶0023) electrically connected to the second impurity regions (12a2) by the plurality of additional pads (S1) (¶0023),
wherein the plurality of direct contacts (202) is arranged in the first horizontal direction (D2; as BL and 202 are arranged as a stack and in D2), and
wherein lower surfaces of the first trench (SC) and lower surfaces of the second trench (R1) are concave with respect to an upper surface of the substrate (as shown in Fig. 8, where SC is concave; and as described in ¶0022, wherein R1 may also be concave [not shown in figure 8]).
Regarding Claim 8, Feng discloses the semiconductor device of claim 7, wherein the plurality of additional pads (S1) is disposed on an inner wall of the first trench (inside of SC) and an outer wall of the second trench (S1 is disposed on an outer wall of R1).
Regarding Claim 9, Feng discloses the semiconductor device of claim 7, wherein a depth of the first trench (SC) is less than a depth of the second trench (R1), relative to the substrate (10) (as shown in Fig. 8).
Regarding Claim 10, Feng discloses the semiconductor device of claim 7, wherein a width (W1) of the first trench (SC) is at least equal to or greater than a width (W2) of the second trench (R1) at a same vertical level (where SC and R1 meet), relative to the substrate (10) (Fig. 8).
Regarding Claim 12, Feng discloses the semiconductor device of claim 7, wherein the plurality of additional pads (S1) comprises a first polysilicon layer (¶0023).
Regarding Claim 17, Feng discloses a semiconductor device (Fig. 1, Fig. 4, and Fig. 9) comprising:
a substrate (10; ¶0013);
a plurality of active regions (12; ¶0013) extending in an oblique direction (D1) in the substrate (10) and spaced apart from each other in a first horizontal direction (D2);
a plurality of word lines (WL; ¶0015) crossing the plurality of active regions (12) in the first horizontal direction (D2) and separating each of the plurality of active regions (12) into a first impurity region (12a1) and second impurity regions (12a2) (¶0014-¶0015) spaced apart from each other with the first impurity region (12a1) therebetween (Fig. 1);
a plurality of bit lines (204 of BL; ¶0017) extending in a second horizontal direction (D3) crossing the first horizontal direction (D2) on the substrate and electrically connected to the first impurity regions (12a1) by a plurality of direct contacts (202; ¶0017) (Fig. 9), respectively;
a first trench (SC; ¶0019) extending in the first horizontal direction and exposing the second impurity regions (12a2) of two adjacent active regions (12) among the plurality of active regions (as described in ¶0019);
a second trench (R1; ¶0020) extending in the first horizontal direction, having a width equal to or narrower than that of the first trench (SC) in the second horizontal direction at a same vertical level, relative to the substrate (10), and passing through a lower surface of the first trench (SC) (as shown in Fig. 8 wherein second trench R1 has a smaller/narrower width W2 than first trench SC with width W1);
a plurality of additional pads (S1; ¶0023) disposed inside the first trench (SC) and outside the second trench (R1) (wherein S1 is inside the first trench SC and outside the second trench R1, wherein this claim limitation does not require S1 to not exist inside the second trench R1), the plurality of additional pads (S1), respectively including a first polysilicon layer; and
a plurality of buried contacts (M1; ¶0023) electrically connected to the second impurity regions (12a2) by the plurality of additional pads (S1) (¶0023), respectively,
wherein each of the plurality of additional pads (S1) comprises a first surface (Annotated Fig. 9; surf1) that overlaps one of the plurality of word lines (WL) in a vertical direction (up/down in Fig. 9), and a second surface (Annotated Fig. 9; surf2) that is free of overlap with the plurality of word lines (WL) in the vertical direction, and
wherein the first surface (surf1) meets the second surface (surf2) at a cusp (Annotated Fig. 9; cusp).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li-Wei Feng et al. (US 20230309291 A1; hereinafter Feng).
Regarding Claim 13, Feng discloses the semiconductor device of claim 12, wherein the plurality of buried contacts (M1) comprises a first metal conductive layer (¶0023).
Feng does not expressly disclose wherein the first metal conductive layer (of M1) is spaced apart from the first polysilicon layer (of S1) with a first silicide film therebetween.
However, Feng discloses in ¶0017 using a (not shown) silicide layer between a semiconductor layer (as in S1) and a metal layer (as in M1). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a silicide layer between the semiconductor and metal layers (as done in ¶0017) of the buried contacts/additional pads in order to form an ohmic contact to reduce resistance.
Allowable Subject Matter
Claims 4-5, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, Feng discloses the semiconductor device of claim 1 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein the cusp is free of overlap with an upper surface of the additional pad (S1) in the vertical direction. As shown in Feng Fig. 9, the cusp overlaps the upper surface of S1. For at least this reason, claim 5 would also be allowable due to its dependence from claim 4.
Regarding Claim 11, Feng discloses the semiconductor device of claim 7 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein a pair of additional pads among the plurality of additional pads adjacent to each other in the oblique direction within the first trench are separated by the second trench. As shown in Fig. 9 of Feng, there is not a pair of additional pads within the first trench SC separated by a second trench.
Regarding Claim 20, Feng discloses the semiconductor device of claim 17 (see above). However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein a pair of additional pads among the plurality of additional pads adjacent in the oblique direction within the first trench are separated by the second trench. As shown in Fig. 9 of Feng, there is not a pair of additional pads within the first trench SC separated by a second trench.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights