DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, Species I, and Species III in the reply filed on 02/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 3, 9, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claims 1-2, 4-8, and 10-16 have been fully considered in Examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/07/2024 and 05/03/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it exceeds 150 words in length (172 words > 150 words). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Drawings
Figure 1 and Figure 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) in view of Ramaswamy (U.S. PG Pub No US2018/0197949A1).
Regarding claim 1, Lu teaches a method [see fig. 1, 0025] used in forming an array of capacitors (double sided capacitor structure arranged in array) [see fig. 2L, 0025, 0031, 0073-0075], comprising:
forming a stack (20) fig. 2A [0029-0031] comprising sacrificial material (202, 204) fig. 2A [0030] (such as silicon dioxide [0031]) and insulative material (203) fig. 2A [0030-0031] (such as silicon nitride [0031]; as evidence that silicon nitride is recognized as an ‘insulative’ material across the art, see further discussion below) that is between a top (204) and a bottom (202) of the sacrificial material [0030];
the insulative material (203) at least predominately comprising at least one of a silicon nitride [0031];
forming horizontally-spaced openings (22) fig. 2A [0032] (at least) partially through the sacrificial material (202, 204);
depositing a lining (23) fig. 2B [0033-0034, 0049] (23 lines border of opening 22/ sidewalls of stack 20, may be formed of silicon dioxide insulator [0031, 0049]) within the horizontally-spaced openings (22) and directly above [see fig. 2B] the sacrificial material (202, 204) [0031];
after depositing the lining (23), extending the horizontally-spaced openings (by removing bottom of 23 [see fig. 2C, 0034]) through remaining of the sacrificial material (202, 204) (bottom of 23 removed by etching, in figs. 2B-2C, thereby extending open space of opening 22 which passes through 202, 204) [0034], the extended horizontally-spaced openings (22 of fig. 2C [0034]) extending (at least partially) through the insulative material (203), the insulative material (203) with extended horizontally-spaced openings (22 of fig. 2C [0034]) there-through comprising an insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings);
forming first capacitor electrodes (electrode layers 24) fig. 2D [0036] (one of ordinary skill in the art would recognize capacitor structure formed with conductive electrodes 24, 30 sandwiching dielectric layer 292 in the completed structure) [see fig. 2K-2L, 0058-0060, 0063] that are individually within (individuated 24 layers formed in fig. 2F [0044]) individual of the extended horizontally-spaced openings (22) laterally over the lining (23) that is in the extended horizontally-spaced openings (22);
removing the sacrificial material (202, 204) fig. 2H [0045] and forming a capacitor [dielectric material] (292) fig. 2I [0056-0058] (“[dielectric material]” added for Examination purposes; 292 is “dielectric material with a high dielectric constant” [0058]) over (above) the first capacitor electrodes (24) and the insulative horizontal lattice (periodic arrangement of 203 material); and
forming second-capacitor-electrode material (30) fig. 2K [0053] (second electrode 30 in capacitor hole) [0058] over the capacitor [dielectric material] (292) (one of ordinary skill in the art would recognize capacitor structure formed with conductive electrodes 24, 30 sandwiching dielectric layer 292 in the completed structure) [see fig. 2K-2L, 0058-0060, 0063].
While Lu does not explicitly disclose that “silicon nitride” in an “insulator” material, [0025] of Ramaswamy (U.S. PG Pub No US2018/0197949A1) evidences that “silicon nitride” is typically considered as an “insulative” material in the art. Further, claim 1 itself defines “the insulative material” as predominately comprising “silicon nitride”.
However, Lu does not explicitly disclose that the capacitor [dielectric material] (292) is an “insulator” material (“dielectric material with a high dielectric constant” [0058] is used to form 292, however, it is not explicitly described as an “insulator” material, nor is its specific chemical composition disclosed).
Ramaswamy teaches a method [0001, 0016] wherein the capacitor dielectric material (28) fig. 1 [0025] (high-k dielectric material such as aluminum oxide [0025]) is a “capacitor insulative material” (28) [0025].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that the capacitor dielectric material with a high dielectric constant is explicitly formed a capacitor “insulative” material [0025] such as aluminum oxide [0025] in order to ensure a suitable insulative composition for the dielectric material of the capacitor [0025] according to art recognized materials [0025], as taught by Ramaswamy.
Regarding claim 2, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. Lu also teaches wherein the horizontally-spaced openings (22) fig. 2A [0032-0034] are formed to extend through the insulative material (203) fig. 2A [0030-0031] (silicon nitride) [0031] prior to depositing the lining (23) fig. 2B [0033].
Regarding claim 4, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. Lu also teaches wherein the insulative material (203) fig. 2A [0030-0031] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings) at least predominately comprise the silicon nitride (only ‘silicon nitride’ explicitly mentioned for 203) [0030-0031].
Regarding claim 8, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. Lu also teaches wherein the lining (23) fig. 2B [0033] is deposited aside (bordering sidewalls of) the insulative horizontal lattice (lattice pattern defined in cross-section by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings).
Regarding claim 10, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. Lu also teaches comprising removing all of the lining (23) fig. 2H [0033] [see fig. 2H, 0045] prior to forming the capacitor insulator (292) fig. 2K [0058].
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) modified by Ramaswamy (U.S. PG Pub No US2018/0197949A1), as applied in claim 1 above, and further in view of Kang (U.S. PG Pub No US2022/0037325A1).
Regarding claim 5, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. However, Lu does not explicitly disclose wherein the insulative material (203) fig. 2A [0030-0031] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings) at least predominately comprise the silicon boronitride (predominantly silicon nitride instead [0030-0031]).
Kang teaches a method [0114] wherein the insulative material (105) fig. 12 [0036, 0114] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 13 by periodically alternating arrangement of horizontally-extending 105 layers relative to H openings [0117, 0120]) at least predominately comprise the silicon boronitride [0036] (instead of silicon nitride [0036]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that the insulative material defining the insulative horizontal lattice is formed of silicon boronitride instead of merely silicon nitride [0036] in order to selectively enhance the etch stopping properties of the insulative film [0036] over the course of the method processing steps [0114], as taught by Kang.
Regarding claim 6, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. However, Lu does not explicitly disclose wherein the insulative material (203) fig. 2A [0030-0031] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings) at least predominately comprise the silicon carbonitride (predominantly silicon nitride instead [0030-0031]).
Kang teaches a method [0114] wherein the insulative material (105) fig. 12 [0036, 0114] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 13 by periodically alternating arrangement of horizontally-extending 105 layers relative to H openings [0117, 0120]) at least predominately comprise the silicon carbonitride [0036] (instead of silicon nitride [0036]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that the insulative material defining the insulative horizontal lattice is formed of silicon carbonitride instead of merely silicon nitride [0036] in order to selectively enhance the etch stopping properties of the insulative film [0036] over the course of the method processing steps [0114], as taught by Kang.
Regarding claim 7, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. However, Lu does not explicitly disclose wherein the insulative material (203) fig. 2A [0030-0031] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings) at least predominately comprise at least two of the silicon nitride, the silicon boronitride, and the silicon carbonitride (only silicon nitride mentioned [0030-0031]).
Kang teaches a method [0114] wherein the insulative material (105) fig. 12 [0036, 0114] and the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 13 by periodically alternating arrangement of horizontally-extending 105 layers relative to H openings [0117, 0120]) at least predominately comprise at least two of the silicon nitride [0036], the silicon boronitride [0036], and the silicon carbonitride [0036] (instead of silicon nitride [0036]) (105 may include silicon nitride, silicon boronitride, and/or silicon carbonitride [0036]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that the insulative material defining the insulative horizontal lattice is formed of silicon carbonitride and silicon boronitride together instead of merely silicon nitride [0036] in order to selectively enhance the etch stopping properties of the insulative film [0036] over the course of the method processing steps [0114], as taught by Kang.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) modified by Ramaswamy (U.S. PG Pub No US2018/0197949A1), as applied in claim 1 above, and further in view of Wu (U.S. PG Pub No US2018/0308923A1).
Regarding claim 11, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. However, Lu does not explicitly disclose wherein the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material [0030-0031] relative to 22 openings) comprises carbon (carbon presence in silicon nitride material of 203 not disclosed [0030-0031]), the insulative horizontal lattice (203 in fig. 2C onwards) having more carbon immediately-laterally-adjacent individual of the first capacitor electrodes (electrode layers 24) fig. 2D [0036] than laterally-distal therefrom (carbon presence not indicated).
Wu teaches a method [0010] wherein the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2 by periodically alternating arrangement of 41 silicon nitride insulative material [0012] relative to horizontally adjacent openings [0013]) comprises carbon (carbon-doped silicon nitride material [0012]), the insulative horizontal lattice (41 in fig. 2 onwards) having more carbon (at bottom sidewalls of 41B [0015-0016], bordering individual of respective electrodes 24, carbon concentration may be ~10-15% [0016]) immediately-laterally-adjacent individual of the first capacitor electrodes (capacitor electrode layers 61) fig. 3 [0014, 0017] than laterally-distal therefrom (at upper sidewalls of 41A [0015-0016], opposite to individual sidewalls of 41B bordering individual of respective electrodes 24, carbon concentration may be ~6% [0016]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the silicon nitride insulative material of Wu to comprise carbon-doped silicon nitride [0012] with a variable concentration of carbon throughout [0015-0016, 0018] in order to preferably enhance the etching resistance properties of the insulative material [0004, 0015-0016, 0022] for improved control over the aspect ratio [0003] of capacitor structures stacked in a vertical direction [0003-0004], thereby enhancing manufacturing yield of the memory device produced by the method [0003-0004, 0022], as taught by Wu.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) modified by Ramaswamy (U.S. PG Pub No US2018/0197949A1) and Wu (U.S. PG Pub No US2018/0308923A1), as applied in claim 11 above, and further in view of Wu-II (U.S. PG Pub No US2020/0135887A1).
Regarding claim 12, Lu in view of Ramaswamy and Wu teaches the method [see fig. 1, 0025] of claim 11. Lu also teaches wherein the lining (23) fig. 2B [0033] is deposited aside the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material relative to 22 openings), the insulative material (203) fig. 2B [0030-0031] (silicon nitride) of the insulative horizontal lattice (203 material of fig. 2C onwards) that is immediately-laterally-adjacent the individual first capacitor electrodes (electrode layers 24) fig. 2D [0036] (203 immediately laterally adjacent 24 in fig. 2H of Lu).
However, Lu does not explicitly disclose wherein the lining (23) fig. 2B [0033] comprises carbon (only silicon dioxide mentioned [0031, 0049]; carbon presence not indicated), diffusing some of the carbon in the lining (23) into the insulative material (203) of the insulative horizontal lattice (203 of fig. 2C onwards).
Wu-II teaches a method [0015] wherein the lining (600) fig. 13 [0043] comprises carbon (may comprise carbon-doped, silicon-based material [0043]), diffusing some of the carbon (DP [0043-0045]) in the lining (600) into the insulative material (310/311) fig. 14A [0024] (silicon nitride [0024]) of the insulative horizontal lattice (311 insulative material [0024]/remaining portions of 310 defined by opening therethrough; insulative material is positioned immediately-laterally-adjacent the first capacitor electrodes in context of primary reference Lu, as described above).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that the lining beside the insulative material is doped with carbon [0043-0044] which is annealed and diffused into the silicon nitride insulative material of the horizontal lattice [0045] in order to favorably control and lower the dielectric constant of the silicon nitride material of the insulative horizontal lattice [0043, 0045], thereby reducing parasitic capacitance [0075] in the product, as taught by Wu-II.
Regarding claim 13, Lu teaches the method [see fig. 1, 0025] of claim 12. Lu in view of Ramaswamy, Wu, and Wu-II (with reference to Wu-II) also teaches wherein the lining (600) fig. 13 [0043] at least predominately comprises at least one of a silicon carbonitride (may comprise silicon doped with carbon and nitrogen [0043], composition predominately described by SixCyNz formula [0043 Wu-II]).
Regarding claim 14, Lu teaches the method [see fig. 1, 0025] of claim 12. Lu in view of Ramaswamy, Wu, and Wu-II (with reference to Wu) also teaches wherein the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2 by periodically alternating arrangement of 41 silicon nitride insulative material [0012] relative to adjacent openings [0013]) that is immediately-laterally-adjacent the individual first capacitor electrodes (capacitor electrode layers 61) fig. 3 [0014, 0017] has from 0.1 atomic percent to 20.0 atomic percent carbon (carbon concentration of carbon doped silicon nitride [0012] may be ~10-15% [0016], which is within and narrower than the claimed range of 0.1-20 atomic percent).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) modified by Ramaswamy (U.S. PG Pub No US2018/0197949A1), Wu (U.S. PG Pub No US2018/0308923A1), and Wu-II (U.S. PG Pub No US2020/0135887A1), as applied in claim 12 above, and further in view of Tang (U.S. PG Pub No US2021/0013226A1).
Regarding claim 15, Lu in view of Ramaswamy, Wu, and Wu-II teaches the method [see fig. 1, 0025] of claim 12. However, Lu does not explicitly disclose wherein the insulative horizontal lattice (lattice pattern defined in cross-section of fig. 2C by periodically alternating arrangement of horizontally-extending 203 material [0030-0031] relative to 22 openings) that is immediately-laterally-adjacent the individual first capacitor electrodes (electrode layers 24) fig. 2D [0036] has from 1.0 atomic percent to 5.0 atomic percent carbon (carbon presence in silicon nitride 203 [0030-0031] not indicated).
Tang teaches a method [0040] wherein the insulative horizontal lattice (remaining portions of 16 carbon-doped silicon nitride material) fig. 1 [0021] that is immediately-laterally-adjacent the individual first capacitor electrodes (electrode layers 46 of 34) fig. 1 [0025] has from 1.0 atomic percent to 5.0 atomic percent carbon (2-10% atomic percent carbon [0021] in silicon nitride material [0021]).
Although Tang does not specifically disclose the recited range of 1-5 atomic percent carbon – Tang discloses a range of 2-10 atomic percent carbon for the concentration of carbon additive in the silicon nitride insulative layer [0021 Tang]. These ranges substantially overlap. Therefore, in the absence of evidence of criticality for the overlapping but slightly different claimed range, one of ordinary skill in the art would consider the claimed range of 1-5 atomic percent carbon to be sufficiently within the scope of the teachings of Tang [0021]. (See MPEP 2144.05, I).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the silicon nitride insulative material of Lu adjacent the capacitor electrodes of Lu to comprise carbon in a concentration of a few atomic percent carbon [0021] as both undoped silicon nitride and carbon-doped silicon nitride are considered equally suitable substitutes [0021] for the insulative material of the tiers in the capacitor structure [0021-0022], as evidenced by Tang. (See MPEP 2144.06, II).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (U.S. PG Pub No US2022/0037460A1) modified by Ramaswamy (U.S. PG Pub No US2018/0197949A1), as applied in claim 1 above, and further in view of Hu (U.S. PG Pub No US2018/0130869A1).
Regarding claim 16, Lu in view of Ramaswamy teaches the method [see fig. 1, 0025] of claim 1. Lu also teaches wherein the lining (23) fig. 2B [0033-0034, 0049] (23 lines border of opening 22/ sidewalls of stack 20, may be formed of silicon dioxide insulator [0031, 0049]) is a first lining (23) and the extending comprises:
forming the extended horizontally-spaced openings (22) fig. 2C [0032-0034] to extend (at least) partially through the remaining sacrificial material (202, 204) fig. 2A [0030-0031].
However, Lu does not explicitly disclose depositing a second lining within the (at least) partially-extended horizontally-spaced openings (23 of fig. 2C onwards) laterally-over the first lining (24) and directly above the stack (20).
Hu teaches a method (100) fig. 1 [0021] comprising depositing a second lining (216) fig. 2F [0031] (at least partially) within the (at least) partially-extended horizontally-spaced openings (212) fig. 2F [0029] laterally-over the first lining (214) fig. 2F [0031] and directly above the stack (positionally represented by stack comprising 204, 205) fig. 2F [0022].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Lu such that additional liners are formed in the trenches hosting the capacitors [0031-0032] in order to, along with other features, fill space to mitigate the formation of voids [0027, 0031, 0043] during processing steps, thereby lowering contact resistance [0006], reducing capacitance variation [0006], and enhancing integration density [0007] of the finished product, as taught by Hu.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they feature methods of forming capacitor array structures comprising insulative stacks and trench structures.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 05/22/2026
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