DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claim(s) 1-9, in the reply filed on 07/06/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0061908, filed on 02/08/2023.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 02/07/2024, 07/19/2024, and 10/21/2025 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. For an instance, Claim(s) 1 and 9 has the limitations with respect to a manufacturing semiconductor chip at a wafer level. The drawing, Figure 3, where the elements (or steps), S210, S220, S230, and S240 that resembles to the aforementioned claim limitations. However, the drawing, Figure 3, has Foreign characters (as labels) before S210, and after S240 which were not translated to English. Therefore, the Figure 3, in which the Foreign labels must be clearly shown or translated in English. No new matter should be entertained.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office Action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office Action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Method for Manufacturing an Outline-Shaped Semiconductor Chip at a Wafer Level.”
Claim Rejections - 35 USC § 112
Claim(s) 2-3 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 2 have the following limitation: “the method, further comprising: performing one or more processes in which a gas for cooling is not mixed with plasma, after performing a plasma dicing process.” The claim is indefinite because it is unknown whether the “one or more processes” as claimed which includes plasma and not mixing the gas with plasma for cooling, or the “one or more processes” as claimed that does not include the plasma which are further claimed in Claim 3, recites, as the “one or more processes comprises performing at least one of a deposition process or a patterning process” and further the combination of plasma or not. In other words, it is not clear that the plasma is turned OFF after the step S220 and before the step S230, but according to paragraph [0073] of the instant application, after execution of the plasma dicing process step, S220, the blade dicing module, 120 may perform one or more processes in which a gas for cooling is not mixed with plasma (S230) with the indefiniteness as mentioned above.
Claim(s) 3 depends on claim 2. Therefore, Claim 3 is rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, and 9, is/are rejected under 35 U.S.C. 103 as being unpatentable over Bora Baloglu et al, (hereinafter BALOGLU), US 20180082896 A1, in view of Mukta G. Farooq et al, (hereinafter FAROOQ), US 20100019354 A1.
Regarding Claim 1, BALOGLU teaches a method of manufacturing a semiconductor chip at a wafer level (Fig. 1, 100, method of manufacturing a semiconductor package, [0014]), comprising:
performing a plasma dicing process (Fig. 1, 130, dicing (or singulating) the wafer, e.g. plasma etching, [0023], [0028]) based on a predetermined shape of an outline (annotated Figure 2B, singulation street, [0024], [0039]) of each of a plurality of semiconductor chips (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) such that a dicing line along a portion of the outline (annotated Figure 2B, singulation street, [0024], [0039]) extends throughout a wafer (Fig. 2B, 230, partially diced wafer, [0024]); and
performing a blade dicing process (Fig. 1, 160, dicing the encapsulated wafer utilizing a laser or mechanical saw, [0037]) such that a remaining portion of the outline (Fig. 2B, 233/235/237/239, connectors/tabs, [0026], [0041]) of the semiconductor chip (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) comprising a connection area (Fig. 2B, 233/235/237/239, connectors/tabs, [0026], [0041]) between adjacent ones ([0041]) of the semiconductor chips (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) is cut along a straight line (annotated Figure 2D).
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Though BALOGLU teaches a method of manufacturing a semiconductor chip at a wafer level comprising: performing a dicing process via a mechanical saw, BALOGLU does not explicitly disclose a method of manufacturing a semiconductor chip at a wafer level comprising: performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line.
FAROOQ teaches a method of manufacturing a semiconductor chip (Fig. 3, method for creating a semiconductor chip, [0009]) at a wafer level (Figs. 2a/3a, 200/300, semiconductor wafer) comprising: performing a blade dicing process (Figs. 2/3, mechanical saw blade dicing, [0024]) such that a remaining portion of the outline (Figs. 2a/3a, 102, perpendicular dicing channel, [0023]) of the semiconductor chip (Figs. 2a/3a, 210/310) comprising a connection area (Figs. 2a/3a, 220, holes) between adjacent ones of the semiconductor chips (Figs. 2a/3a, 210/310) is cut along a straight line (dicing step, [0009], [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BALOGLU to incorporate the teachings of FAROOQ, such that a method of manufacturing a semiconductor chip at a wafer level comprising: performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line, so that the aforementioned process reduce the delamination initiation and propagation by eliminating semiconductor chips with corners having ninety degree angles (FAROOQ, [0027-0028]).
Regarding Claim 4, BALOGLU as modified by FAROOQ teaches the method according to claim 1.
BALOGLU further teaches the method (Fig. 1, 100, method of manufacturing a semiconductor package, [0014]), further comprising: predetermining the outline portion (Fig. 2B, first portions of the singulation streets maybe left unmasked and subject to etching, [0028]) of each of the plurality of semiconductor chips (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) which is a dicing target (Fig. 1, 130, may comprise utilizing etching (e.g. plasma etching) to dice (e.g. partially dice) the wafer, [0028]).
Regarding Claim 5, BALOGLU as modified by FAROOQ teaches the method according to claim 4,
FAROOQ teaches a method of manufacturing a semiconductor chip (Fig. 3, method for creating a semiconductor chip, [0009]), wherein the predetermined outline portion (Fig. 2a, 102/220, perpendicular dicing channel/holes) of each of the plurality of semiconductor chips (Figs. 2a/3a, 210/310) comprises at least one of a curved line or a bent line (Fig. 2b, 106, triangular zone).
Regarding Claim 9, BALOGLU teaches a semiconductor chip manufactured the method at a wafer level by a method (Fig. 1, 100, method of manufacturing a semiconductor package, [0014]), the method comprising:
performing a plasma dicing process (Fig. 1, 130, dicing (or singulating) the wafer, e.g. plasma etching, [0023], [0028]) based on a predetermined shape of an outline (annotated Figure 2B, singulation street, [0024], [0039]) of each of a plurality of semiconductor chips (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) such that a dicing line along a portion of the outline (annotated Figure 2B, singulation street, [0024], [0039]) extends throughout a wafer (Fig. 2B, 230, partially diced wafer, [0024]); and
performing a blade dicing process (Fig. 1, 160, dicing the encapsulated wafer utilizing a laser or mechanical saw, [0037]) such that a remaining portion of the outline (Fig. 2B, 233/235/237/239, connectors/tabs, [0026], [0041]) of the semiconductor chip (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) comprising a connection area (Fig. 2B, 233/235/237/239, connectors/tabs, [0026], [0041]) between adjacent ones ([0041]) of the semiconductor chips (Fig. 2B, 231/232/234/236/238, first/second/third/fourth/fifth die, [0026]) is cut along a straight line (annotated Figure 2D).
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Though BALOGLU teaches a method of manufacturing a semiconductor chip at a wafer level comprising: performing a dicing process via a mechanical saw, BALOGLU does not explicitly disclose a method of manufacturing a semiconductor chip at a wafer level comprising: performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line.
FAROOQ teaches a method of manufacturing a semiconductor chip (Fig. 3, method for creating a semiconductor chip, [0009]) at a wafer level (Figs. 2a/3a, 200/300, semiconductor wafer) comprising: performing a blade dicing process (Figs. 2/3, mechanical saw blade dicing, [0024]) such that a remaining portion of the outline (Figs. 2a/3a, 102, perpendicular dicing channel, [0023]) of the semiconductor chip (Figs. 2a/3a, 210/310) comprising a connection area (Figs. 2a/3a, 220, holes) between adjacent ones of the semiconductor chips (Figs. 2a/3a, 210/310) is cut along a straight line (dicing step, [0009], [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BALOGLU to incorporate the teachings of FAROOQ, such that a method of manufacturing a semiconductor chip at a wafer level comprising: performing a blade dicing process such that a remaining portion of the outline of the semiconductor chip comprising a connection area between adjacent ones of the semiconductor chips is cut along a straight line, so that the aforementioned process reduce the delamination initiation and propagation by eliminating semiconductor chips with corners having ninety degree angles (FAROOQ, [0027-0028]).
Claim(s) 2, is/are rejected under 35 U.S.C. 103 as being unpatentable over BALOGLU, in view of FAROOQ as applied to claim(s) 1, 4-5 and 9, and further in view of Thomas Rohleder et al, (hereinafter ROHLEDER), US 20170092540 A1.
Regarding Claim 2, BALOGLU as modified by FAROOQ teaches the method according to claim 1.
BALOGLU further teaches the method (Fig. 1, 100, method of manufacturing a semiconductor package, [0014]), further comprising: performing one or more processes (Fig. 1, 140, encapsulate diced wafer, [0031]) in which a gas for cooling is not mixed with plasma (Fig. 1, 140, per paragraph [0031] and [0033], the encapsulating the wafer in an encapsulant comprise utilizing a transfer molding process, a compression molding process, an injection molding process etc. that does not require a gas for cooling is not mixed with plasma as claimed) after the performing a plasma dicing process (Fig. 1, 130, dicing (or singulating) the wafer, e.g. plasma etching, [0023], [0028]).
Though BALGOLU teaches the method, other than a plasma process (or an encapsulation process with no plasma involved) after the performing a plasma dicing process, BALGOLU does not explicitly disclose the method, further comprising: performing one or more processes in which a gas for cooling is not mixed with plasma after the performing a plasma dicing process.
ROHLEDER teaches the method (Fig. 1, 100, process prepares the wafer substrate, [0024]), further comprising: performing one or more processes (Fig. 1, 170, additional plasma etch through inter-metal dielectric at saw lanes to separate device die, [0028]) in which a gas for cooling is not mixed with plasma (Fig. 1, 170, additional plasma etch through inter-metal dielectric at saw lanes to separate device die, [0028]) after the performing a plasma dicing process (Fig. 1, 160, plasma etch bulk silicon to depth on inter-metal dielectric at saw lanes, [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BALOGLU as modified by FAROOQ to incorporate the teachings of ROHLEDER, such that the method, further comprising: performing one or more processes in which a gas for cooling is not mixed with plasma after the performing a plasma dicing process, so that after manufacturing, the wafer containing from hundreds to thousands to device die, has to be diced up into individual active devices with an aforementioned efficient process to performing the dicing to maintain acceptable yields and contain costs (ROHLEDER, [0004]).
Claim(s) 3, is/are rejected under 35 U.S.C. 103 as being unpatentable over BALOGLU, in view of FAROOQ and ROHLEDER as applied to claim(s) 2, and further in view of Wei-Sheng Lei, (hereinafter LEI), US 20140179084 A1.
Regarding Claim 3, BALOGLU as modified by FAROOQ and ROHLEDER teaches the method according to claim 2.
Though BALOGLU teaches an encapsulation process after plasma etch dicing of a semiconductor package, BALOGLU as modified by FAROOQ and ROHLEDER does not explicitly disclose the method, wherein the performing one or more processes comprises performing at least one of a deposition process or a patterning process.
LEI teaches the method (Fig. 1, 100, flowchart including operations for a backside laser plus plasma etch dicing process, [0024]), wherein the performing one or more processes comprises performing at least one of a deposition process or a patterning process (Fig. 1, 112, apply dicing tape on the backside of the wafer, [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BALOGLU as modified by FAROOQ and ROHLEDER to incorporate the teachings of LEI, such that the method, wherein the performing one or more processes comprises performing at least one of a deposition process or a patterning process, so that a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma treatment to yield clean die or chip singulation or dicing (LEI, [0021]).
Claim(s) 6-8, is/are rejected under 35 U.S.C. 103 as being unpatentable over BALOGLU, in view of FAROOQ as applied to claim(s) 1, 4-5 and 9, and further in view of Taehyun Kim et al, (hereinafter KIM), US 20190189419 A1.
Regarding Claim 6, BALOGLU as modified by FAROOQ teaches the method according to claim 5.
BALOGLU as modified by FAROOQ does not explicitly disclose the method, wherein each of the plurality of semiconductor chips is an ion trap chip configured to trap ions.
KIM teaches the method (Fig. 14, method of manufacturing an ion trap chip, [0061]), wherein each of the plurality of semiconductor chips (Fig. 15, 410, semiconductor substrate, [0043-0044]) is an ion trap chip (Fig. 13, 400, ion trap chips) configured to trap ions (Fig. 13, 480, ion trapping zone, [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BALOGLU as modified by FAROOQ to incorporate the teachings of KIM, such that the method, wherein each of the plurality of semiconductor chips is an ion trap chip configured to trap ions, so that 3D ion trap chip design to reduce an influence of the laser scattering in the ion trap process (KIM, [0075]).
Regarding Claim 7, BALOGLU as modified by FAROOQ teaches the method according to claim 6.
BALOGLU further teaches the method (Fig. 1, 100, method of manufacturing a semiconductor package, [0014]), wherein the performing a plasma dicing process (Fig. 1, 130, dicing (or singulating) comprises dicing the outline portion (Fig. 2B, first portions of the singulation streets maybe left unmasked and subject to etching, [0028]).
KIM further teaches the method (Fig. 14, method of manufacturing an ion trap chip, [0061]), wherein the performing each of the ion trap chips (Fig. 13, 400, ion trap chips) to reduce or remove scattering of a laser (Fig. 17, ion trap chip device to reduce an influence of the laser scattering in the ion trap, [0075]) when ions are trapped (Fig. 13, 480, ion trap zone, [0044]) at an upper surface of the ion trap chip (Fig. 12, 400, ion trap chip, [0053]).
Regarding Claim 8, BALOGLU as modified by FAROOQ teaches the method according to claim 1.
BALOGLU as modified by FAROOQ does not explicitly disclose the method, wherein the semiconductor chip is a microelectromechanical system (MEMS) chip.
KIM teaches the method (Fig. 14, method of manufacturing an ion trap chip, [0061]), wherein the semiconductor chip (Fig. 15, 410, semiconductor substrate, [0043-0044]) is a microelectromechanical system (MEMS) chip (Figs. 3/4, MEMS-based 3D ion trap chip, [0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BALOGLU as modified by FAROOQ to incorporate the teachings of KIM, such that the method, wherein the semiconductor chip is a microelectromechanical system (MEMS) chip, since the introduction of the concept of applying the ion trap to the quantum computer, MEMS-based 3D ion trapping technology thus generally increase the life of the ion by securing more potential depth (KIM, [0008-0009]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210013043 A1 – Figures 5A-5D
STATEMENT OF RELEVANCE – The plasma dicing method with respect to a first portion of the substrate, 10.
US 20050061767 A1 – Figures 3
STATEMENT OF RELEVANCE – Flow chart illustrating a method of fabricating arrays of quadrupole ion traps on a wafer.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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