DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-24 in the reply filed on 4/14/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/7/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-10, 12-16 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marimuthu et al. US 2019/0088603.
Re claim 1, Marimuthu teaches a semiconductor package (330, fig5, [70]), comprising:
a semiconductor chip (124, fig5, [70]) comprising multiple radio frequency channels (124 for RF process connected with antenna 352, fig5, [35, 70]);
a signal port (174 connected with 360/212A in 340/342, fig3e, 3h and 5, [51, 70]) arranged external to the semiconductor chip (124, fig5, [70]) and associated with one of the multiple radio frequency channels (132 of 124, fig3h, [36]); and
a shielding structure (174 around 360/212A in 340/342, fig3h and 5, [51, 70]) at least partially surrounding the signal port (174 connected with 360/212A in 340/342, fig3h and 5, [70]) when viewed in a first direction (fig5),
wherein the shielding structure is configured to reduce a propagation of an interference signal at least from or to the signal port in a second direction (second direction extend in plane of fig5) perpendicular to the first direction (Z, fig5) ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Marimuthu teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.).
Re claim 2, Marimuthu teaches the semiconductor package of claim 1, further comprising: an encapsulation material (190 and 170, fig3h, [48]) at least partially encapsulating the semiconductor chip (124, fig3h, [70]), wherein the shielding structure (174 around 360/212A in 340/342, fig3h and 5, [51, 70]) is arranged in the encapsulation material and is configured to reduce the propagation of the interference signal through the encapsulation material in the second direction.
Re claim 3, Marimuthu teaches the semiconductor package of claim 1, further comprising: a ball grid array substrate (200 with 206, fig3h, [61, 62]), wherein the shielding structure is arranged in the ball grid array substrate and is configured to reduce the propagation of the interference signal through the ball grid array substrate in the second direction.
Re claim 4, Marimuthu teaches the semiconductor package of claim 1, wherein the shielding structure comprises an electrically conductive material (conductive via 174 filled with Cu around 360/212A in 340/342, fig3h and 5, [45, 70]).
Re claim 5, Marimuthu teaches the semiconductor package of claim 1, wherein the shielding structure is formed by one or multiple three-dimensional metal components (conductive via 174 around 360/212A in 340/342, fig3h and 5, [45, 70]).
Re claim 6, Marimuthu teaches the semiconductor package of claim 5, wherein the one or multiple three-dimensional metal components comprise at least one of a metal via (conductive via 174 filled with Cu around 360/212A in 340/342, fig3h and 5, [45, 70]), a metal strip, a metal bar, a metal wall, or a metal mesh.
Re claim 9, Marimuthu teaches the semiconductor package of claim 1, wherein the shielding structure is configured to provide an electrical shielding between the signal port and an adjacent signal port associated with a further radio frequency channel of the multiple radio frequency channels ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Marimuthu teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.).
Re claim 10, Marimuthu teaches the semiconductor package of claim 1, wherein the signal port comprises a ground line portion (174 connected with ground plane 350/202B on the back, fig3i,3h and 5, [60, 70]) at least partially surrounding a signal line portion (174 connected with 360/212A in region between 202B, fig3i, 3h and 5).
Re claim 12, Marimuthu teaches the semiconductor package of claim 1, further comprising: an electrical redistribution layer (210 and 214, fig3h, [53) comprising a signal line (212A/360, fig3e, 3h and 5), wherein the signal line provides an electrical connection between the signal port (174 connected with 360/212A in 340/342, fig3e, 3h and 5, [70]) and the semiconductor chip (124, fig5, [70]), and wherein the shielding structure (174 around 360/212A in 340/342, fig3h and 5, [51, 70]) at least partially surrounds the signal line (212A/360, fig3e, 3h and 5).
Re claim 13, Marimuthu teaches the semiconductor package of claim 12, wherein: the shielding structure exclusively surrounds the signal port (174 surround 174 connected with 360/212A, fig 3h and 5), or the shielding structure exclusively surrounds the signal port and the signal line.
Re claim 14, Marimuthu teaches the semiconductor package of claim 1, wherein the shielding structure is electrically connected to a non-floating electrical potential (174 around 360/212A in 340/342 coupled to ground reference voltage signal, fig3h and 5, [70]).
Re claim 15, Marimuthu teaches the semiconductor package of claim 12, wherein the shielding structure is electrically connected to a ground metallization of the electrical redistribution layer (174 around 360/212A in 340/342 coupled to ground reference voltage signal, fig3h and 5, [70]).
Re claim 16, Marimuthu teaches the semiconductor package of claim 1, further comprising: an external connection element (212A/360, fig3h and 5, [51, 70]) configured to mechanically and electrically connect the semiconductor package (124, fig5, [70]) to a printed circuit board (340/342, fig5, [70]), wherein the external connection element (212A/360, fig3h and 5, [51, 70]) at least partially overlaps the shielding structure when viewed in the first direction (174 around 360/212A in 340/342, fig3h and 5, [51, 70]).
Re claim 23, Marimuthu teaches the semiconductor package of claim 1, wherein the signal port and the shielding structure are laterally displaced to the semiconductor chip when viewed in the first direction (fig5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Marimuthu et al. US 2019/0088603 in view of Ebefors et al. US 2015/0255344.
Re claim 7, Marimuthu does not explicitly show the semiconductor package of claim 1, wherein the shielding structure comprises a semiconductor material.
Ebefors teaches a method of forming TSV by forming a poly-silicon layer (22, fig5, [68]) followed by filling the hole with metal (28, fig7, [72]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Marimuthu and Ebefors to form via 174 with the method of Ebefors. The motivation to do so is to fill high aspect ratio via hole with cost effective process and improve wetting capability during metal filling process (Ebefors, [52]).
Re claim 8, Marimuthu teaches the semiconductor package of claim 7, wherein the semiconductor material comprises multiple trenches filled with a mold compound (Marimuthu, epoxy of 172 between 174 with poly silicon in region 342/340, fig3h).
Allowable Subject Matter
Claim 11, 17-22 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to improved isolation properties between the individual radar signal channels.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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