DETAILED ACTION
This action is responsive to the election received on 05/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 05/26/2026 is acknowledged.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 01/25/2024.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/02/2025 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 26-28 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 26 recites the limitation "a second p-type epitaxial region of the substrate region is between . . ." in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim. It is unclear if the substrate region is a new element not previously identified, as there has been no previous recitation of “a substrate region”, or if the intention of the limitation is to refer to the substrate as a whole which has previously been identified in claim 24, line 2. Therefore, claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, and claim(s) 27-28 is/are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, claim 26 will be interpreted to read as "a second p-type epitaxial region of the substrate is between . . .".
Regarding claim 27, the term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "in a substantial manner” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how similar the widths of the p-type epitaxial regions need to be in order to have substantially a same width. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries explicitly. The specification provides only in [0012] that “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range” which includes several possible target ranges. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, 20%, or some other percentage) or within a certain number of units of the target (such as several nm, µm, or mm), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, claim 27 is rejected as being indefinite under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the purposes of this examination, it will be interpreted that any two p-type epitaxial regions have substantially the same width, regardless of the differences in their respective widths, as no clear boundaries have been provided.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16-19, 21-22, and 24-35 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0266351 A1; Okamoto et al.; 08/2024; (“Okamoto”).
Regarding Claim 16. Okamoto discloses A method (Figures 6-12, [0058]-[0072] where the modification of Figure 16 is considered herein), comprising:
forming a substrate (#SB, Figures 6-7, semiconductor substrate) having a p-type substrate region (#BBL, Figure 7, buried base layer which is p-type according to [0045]) and a p-type epitaxial layer (#BL, Figure 7, base layer which is p-type epitaxial according to [0063]) over the p-type substrate region (Figure 7, #BL is formed over #BBL);
forming an isolation structure (#ISO, Figure 16, [0083], an isolation region of the substrate may be formed as a modification to the method) in the substrate (Figure 16, #ISO is formed in #SB);
performing a first implantation process (Figures 8-9, [0064]-[0066], a plurality of n-type implantations which may together be interpreted as a first implantation process) to form first (#RDN, Figure 9), second (#NW, Figure 9), and third (#RSU, Figure 9) n-type regions in the p-type epitaxial layer (Figure 9, [0064]-[0066], #RDN, #NW, and #RSU are all n-type regions formed in #BL), the second n-type region being between the first and third n-type regions (Figure 9, #NW is located laterally between #RSU and #RDN),
wherein the p- type epitaxial layer (#BL) has a first remaining portion between the first and second n-type regions (Figure 16, let the portion of #BL to the left #ISO be a first remaining portion of #BL that is located at least partially between #RDN and #NW), and a second remaining portion between the second and third n-type regions (Figure 9, let the portion of #BL to the right of #ISO be a second remaining portion of #BL that is located at least partially between #RSU and #NW);
performing a second implantation process (Figures 8-9, [0064]-[0066], a plurality of p-type implantations which may together be interpreted as a second implantation process) to form a p-type doped region in the third n-type region (#RPU, Figure 9, p-type region which is located at least partially within #RSU); and
forming a drain electrode (#EDN, Figure 16, drain electrode), a gate electrode (#EGU, Figure 16, gate electrode), and a source electrode (#ESP, Figure 16, source electrode) over the substrate (Figure 16, #EDN, #EGU, and #ESP are all formed over at least a portion of #SB), wherein the drain electrode is electrically coupled to the first n-type region (Figure 16, #EDN is directly electrically coupled to #RDN), the gate electrode is electrically coupled to the p-type doped region (Figure 16, #EGU is electrically coupled #RPU as being part of the UMOS transistor), and the source electrode is electrically coupled to the second n-type region (Figure 16, #ESP is electrically coupled to #RNW as being part of the PMOS transistor).
Regarding Claim 17. Okamoto discloses The method of claim 16, wherein the first and second remaining portions extend from the p-type substrate region to the isolation structure (Figure 16, the remaining portions of #BL to the left and right of #ISO may be bounded as necessary to extend from the #ISO region to #BBL since the only other required boundaries are that they extend between the respective n-type regions as required of claim 16 and there are not boundaries to the word portion).
Regarding Claim 18. Okamoto discloses The method of claim 16, wherein the first and second remaining portions have a ring-shape top profile (Figure 16, the remaining portions of #BL to the left and right of #ISO may be bounded as necessary to have a ring shape in a top view since the only other required boundaries are that they extend between the respective n-type regions as required of claim 16 and there are not boundaries to the word portion).
Regarding Claim 19. Okamoto discloses The method of claim 16, further comprising:
forming a dielectric layer (#IL, Figure 16, interlayer dielectric film) over the isolation structure (Figure 16, #IL is formed at least partially over the #ISO region); and
forming a conductive plate (#ESU, Figure 16, source electrode) over the dielectric layer (Figure 16, #ESU is formed over at least a portion of #IL in the #ARU region), wherein the conductive plate is spaced apart from the gate electrode (Figure 16, #ESU is spaced apart from #EGU).
Regarding Claim 21. Okamoto discloses The method of claim 19, wherein the conductive plate is laterally offset from the second remaining portion of the p-type epitaxial layer by a non-zero distance (Figure 16, the remaining portion of #BL to the right of #ISO be bounded on its right side by #RSU since the only other required boundaries are that they extend between the respective n-type regions as required of claim 16 and there are not boundaries to the word portion, the portion of #BL as bounded is laterally offset from #ESU at least by a distance covering a portion of #RSU).
Regarding Claim 22. Okamoto discloses The method of claim 16, further comprising performing a third (Examiner note: use of the word third here does not require occurrence after first and second) implantation process ([0061]) to form a deep p-well region (#BBL1, Figure 6) in the p-type substrate region (#BBL1, Figure 6, [0061], buried base layer formed by p-type implantation to be in the #BBL region), wherein the deep p-well region vertically overlaps the p-type doped region (Figure 16, #BBL1 at least partially overlaps with #RPU.
Regarding Claim 24. Okamoto discloses A method (Figures 6-12, [0058]-[0072] where the modification of Figure 16 is considered herein), comprising:
forming an isolation structure (#ISO, Figure 16, [0083], an isolation region of the substrate may be formed as a modification to the method) in a substrate (#SB, Figure 16, #ISO is formed in substrate #SB);
forming a first n-type region (#RDN, Figure 9) and a second n-type region (#RSU, Figure 9) in the substrate (Figure 9, [0064]-[0066], #RDN and #RSU are n-type regions formed in #BL of #SB), such that a first p-type epitaxial region (#BL, Figure 7, base layer which is p-type epitaxial according to [0063]) of the substrate is between the first n-type region and the second n-type region (Figure 16, portions of #BL are located between #RDN an #RSU), wherein in a cross-sectional view the first p-type epitaxial region is vertically below the isolation structure (Figure 16, portions of #BL are vertically below the region identified as #ISO);
forming a p-type doped region within the second n-type region (#RPU, Figure 9, p-type region which is located at least partially within #RSU); and
forming a drain electrode (#EDN, Figure 16, drain electrode) electrically coupled to the first n-type region (Figure 16, #EDN is directly electrically coupled to #RDN),
a gate electrode (#EGU, Figure 16, gate electrode) electrically coupled to the p-type doped region (Figure 16, #EGU is electrically coupled to #RPU as part of #UMOS), and
a source electrode (#ESU, Figure 16, source electrode) electrically coupled to the second n-type region (Figure 16, #ESU is directly electrically coupled to #RSU).
Regarding Claim 25. Okamoto discloses The method of claim 24, wherein forming the first n-type region and the second n-type region further comprises forming a third n-type region (#NW, Figure 9) in the substrate (Figure 9, [0064]-[0066], #RDN, #NW, and #RSU are all n-type regions formed in #BL) and laterally between the first n-type region and the second n-type region (Figure 16, #NW is laterally between #RDN and #RSU).
Regarding Claim 26. Okamoto discloses The method of claim 25, wherein a second p-type epitaxial region of the substrate is between the first and second n-type regions (Figure 16, let the portion of #BL to the left of #NW be the second portion and the portion of #BL to the right be the first portion which is under the region labelled #ISO, both of which are at least partially between #RDN and #RSU), the first p-type epitaxial region and the second p-type epitaxial region are laterally spaced apart from each other through the third n- type region (Figure 16, the portions of #BL to the left and right of #NW are necessarily laterally spaced apart by #NW).
Regarding Claim 27. Okamoto discloses The method of claim 26, wherein in the cross-sectional view the first and second p-type epitaxial regions have substantially a same width (Figure 16, based on the interpretation described above for the word substantially, it is interpreted that the portions of #BL to the left and right of #NW have substantially the same width).
Regarding Claim 28. Okamoto discloses The method of claim 26, wherein in a top view the first p-type epitaxial region and the second p-type epitaxial region include a ring-shape top profile (Figure 16, the remaining portions of #BL to the left and right of #NW may be bounded as necessary to have a ring shape in a top view since the only other required boundaries are that they extend between the respective n-type regions as required of claims 24 and 26 and there are not boundaries to the word portion), and wherein the second p- type epitaxial region surrounds the first p-type epitaxial region (Figure 16, the portion of #BL to the left of #NW at least partially surrounds the portion of #BL to the right of #NW).
Regarding Claim 29. Okamoto discloses The method of claim 24, further comprising forming a polysilicon plate (#EGD, Figure 16, gate electrode which is formed in a similar manner to #EGU according to [0083] and #EGU is made of polysilicon according to [0047]) over the isolation structure (Figure 16, #EGD is over at least a side portion of the #ISO structure region), wherein the polysilicon plate is laterally between the drain electrode and the gate electrode (Figure 16, #EGD is laterally between #EGU and #EDN where laterally between does not require overlap).
Regarding Claim 30. Okamoto discloses The method of claim 29, wherein in the cross-sectional view the polysilicon plate overlaps a portion of the p-type doped region (Figure 16, #EGD overlaps a portion of #RPU in a lateral direction of the cross section provided).
Regarding Claim 31. Okamoto discloses The method of claim 30, further comprising forming a dielectric layer (#GID, Figure 16, gate insulating film) over the isolation structure prior to forming the polysilicon plate (Figure 16, [0083], #GID is formed prior to forming #EGD thereon), wherein the dielectric layer is between the polysilicon plate and the isolation structure (Figure 16, #GID is laterally between #EGD and the #ISO structure region).
Regarding Claim 32. Okamoto discloses A method (Figures 6-12, [0058]-[0072] where the modification of Figure 16 is considered herein), comprising:
forming an isolation structure (#ISO, Figure 16, [0083], an isolation region of the substrate may be formed as a modification to the method) in a substrate (#SB, Figure 16, #ISO is formed in substrate #SB);
forming a first n-type region (#RDN, Figure 9) and a second n-type region (#RSU, Figure 9) in the substrate (Figure 9, [0064]-[0066], #RDN and #RSU are n-type regions formed in #BL of #SB), wherein the first n-type region is spaced apart from the second n-type region (Figure 16, #RDN and #RSU are spaced apart from each other in the lateral direction);
forming a p-type doped region within the second n-type region (#RPU, Figure 9, p-type region which is located at least partially within #RSU);
forming a conductive plate (#EGD, Figure 16, gate electrode which is formed in a similar manner to #EGU according to [0083] and #EGU is made of polysilicon according to [0047]) over the isolation structure (Figure 16, #EGD is over at least a side portion of the #ISO structure region); and
forming a drain electrode (#EDN, Figure 16, drain electrode) electrically coupled to the first n-type region (Figure 16, #EDN is directly electrically coupled to #RDN),
a gate electrode (#EGU, Figure 16, gate electrode) electrically coupled to the p-type doped region (Figure 16, #EGU is electrically coupled to #RPU as part of #UMOS), and
a source electrode (#ESU, Figure 16, source electrode) electrically coupled to the second n-type region (Figure 16, #ESU is directly electrically coupled to #RSU),
wherein the conductive plate is laterally between the drain electrode and the gate electrode (Figure 16, #GID is laterally between #EGD and the #ISO structure region where “between” does not require direct overlap).
Regarding Claim 33. Okamoto discloses The method of claim 32, wherein the conductive plate overlaps a boundary between the p-type doped region and the second n-type region (Figure 16, #EGD laterally overlaps a vertical boundary between #RPU and #RSU in the cross section provided).
Regarding Claim 34. Okamoto discloses The method of claim 32, further comprising forming a dielectric layer (#GID, Figure 16, gate insulating film) over the isolation structure prior to forming the conductive plate (Figure 16, [0083], #GID is formed prior to forming #EGD thereon), wherein the dielectric layer is between the conductive plate and the isolation structure (Figure 16, #GID is laterally between #EGD and the #ISO structure region).
Regarding Claim 35. Okamoto discloses The method of claim 32, wherein a p-type epitaxial region (#BL, Figure 7, base layer which is p-type epitaxial according to [0063]) of the substrate (Figure 16, #BL is part of #SB) is laterally between the first n-type region and the second n-type region (Figure 16, portions of #BL are located laterally between #RDN an #RSU).
Allowable Subject Matter
Claim(s) 20 and 23 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches “the second implantation process is performed such that the p-type doped region has a portion extending to a position below the isolation structure, and wherein the conductive plate overlaps the portion of the p-type doped region” as recited in claim 20 and in combination with all of the other required limitations, or “the second implantation process and the third implantation process are performed through a same mask” as recited in claim 23 and in combination with all of the other required limitations.
Regarding Claim 20. Okamoto discloses The method of claim 19.
Okamoto does not disclose that the second implantation process is performed such that the p-type doped region has a portion extending to a position below the isolation structure, and wherein the conductive plate overlaps the portion of the p-type doped region. The p-type doped region (#RPU) and the conductive plate (#ESU) are formed entirely outside of the isolation region (#ISO) in Figure 16 of Okamoto such that no portion of the p-type doped region that may be interpreted as below the isolation structure and overlapped by the conductive plate. Therefore, claim 20 is interpreted as including allowable subject matter and may be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 23. Okamoto discloses The method of claim 22.
Okamoto does not disclose that the second implantation process and the third implantation process are performed through a same mask. The doped regions formed by the second and third implantations processes in Okamoto have entirely different cross-sections such that they cannot be formed by the same mask. Even if it were obvious to use the same mask for the purpose of reducing processing steps, an alternative mask would still be required to address the different areas intended to be doped by the separate implantation processes. Therefore, claim 23 is interpreted as including allowable subject matter and may be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0048672 A1; Takei et al.; 02/2025 – Figures 10A-10N disclose a method of forming a semiconductor device including forming p-type substrate (#12) and epitaxial regions (#13) with isolation structures (#19) and n-type doped regions (#15 and #17) formed thereon to have portions of the p-type epitaxial region between them.
US 2017/0373171 A1; Sadovnikov et al.; 12/2017 – Figures 1 and 2A-2E disclose a method of forming a JFET device including forming p-type substrate (#104) and epitaxial regions (#110) with isolation structures (#134) and n-type doped regions (#108) formed thereon to have portions of the p-type epitaxial region between them and a back gate deep p-type region (#116).
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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