Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Figures 4-10 in the reply filed on 5/20/26 is acknowledged.
Claims 10-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/20/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 12, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jan (US PGPub 2019/0206980).
Claim 1: Jan teaches (Fig. 6, 8A-8B) a semiconductor device, comprising: a substrate (104); an element insulating layer (871), disposed on the substrate; and a semiconductor resistive layer (110), disposed within the element insulating layer, wherein the semiconductor resistive layer extends along a first direction perpendicular to a thickness direction of the substrate and includes an uneven portion along the thickness direction.
Claim 2: Jan teaches (Fig. 6, 8A-8B) the uneven portion is multiply disposed and spaced apart from each other along the first direction.
Claim 3: Jan teaches (Fig. 6, 8A-8B) the plurality of uneven portions are disposed in the same pitch along the first direction.
Claim 4: Jan teaches (Fig. 6, 8A-8B) the uneven portion includes: a first resistive portion, extending along the first direction; a second resistive portion, located at a position shifted from the first resistive portion along the first direction and closer to the substrate than the first resistive portion, wherein the second resistive portion extends along the first direction; and a connecting portion, extending along a direction intersecting the first direction and connecting an end of the first resistive portion along the first direction to an end of the second resistive portion along the first direction.
Claim 5: Jan teaches (Fig. 6, 8A-8B) a length of the second resistive portion is less than a length of the first resistive portion.
Claim 6: Jan teaches (Fig. 6, 8A-8B) a length of the connecting portion is greater than a thickness of the first resistive portion.
Claim 7: Jan teaches (Fig. 6, 8A-8B) a length of the connecting portion is greater than a length of the second resistive portion.
Claim 8: Jan teaches (Fig. 6, 8A-8B) a direction perpendicular to both the first direction and the thickness direction is set as a second direction, and the connecting portion extends obliquely with respect to the thickness direction when viewed from the second direction.
Claim 12: Jan teaches (Fig. 6, 8A-8B) [0035-0041] a wiring layer, electrically connected to the semiconductor resistive layer; and a connecting wiring, connecting the semiconductor resistive layer to the wiring layer, wherein the semiconductor resistive layer is disposed at a position different from a position of the uneven portion along the first direction, and includes a resistive end portion to which the connection wiring is connected.
Claim 15: Jan teaches (Fig. 6, 8A-8B) a semiconductor module, comprising: the semiconductor device of Claim 1; a support member, supporting the semiconductor device; and a sealing resin, sealing the semiconductor device and the support member. Sealing resins and support modules (interposers PCBs etc.) are common components in semiconductor modules.
Claim 16: Jan teaches (Fig. 6, 8A-8B) a semiconductor module, comprising: the semiconductor device of Claim 2; a support member, supporting the semiconductor device; and a sealing resin, sealing the semiconductor device and the support member. Sealing resins and support modules (interposers PCBs etc.) are common components in semiconductor modules.
Claims 9, and 13-14 are rejected under 35 U.S.C. 103 as being obvious by Jan (US PGPub 2019/0206980), as applied to claim 1 above and further in view of Tanaka et al. (US PGPub 2024/0339490/ PCT/JP2022/ 041560)
Regarding claim 9, as described above, Jan substantially reads on the invention as claimed, and Jan teaches a wiring layer electrically connected to the semiconductor resistive layer. Jan does not teach the wiring layer is disposed closer to the substrate than the semiconductor resistive layer along the thickness direction. Tanaka teaches the wiring layer is disposed closer to the substrate than the semiconductor resistive layer along the thickness direction to connect the resistors to each other within the device [0173] Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Jan to have had the wiring layers between the resistor and substrate to connect the resistors to other as taught by Tanaka [0173]
Claim 13: Tanaka teaches the semiconductor resistive layer is multiply disposed, a direction perpendicular to both the first direction and the thickness direction is set as a second direction, and the plurality of semiconductor resistive layers are spaced apart along the second direction[0173]. Multiple instances of the same device within a semiconductor chip is common.
Claim 14: Tanaka teaches the element insulating layer (22) includes: a substrate-side insulating layer (31), disposed on the substrate (21); and a front-side insulating layer, laminated on the substrate-side insulating layer, wherein the substrate-side insulating layer (31) is formed by a plurality of first insulating films (31A) and a plurality of second insulating films (31B) alternately stacked with each other, the second insulating films are configured for relieving stress [0171] of the plurality of first insulating films, and the semiconductor resistive layer is embedded in the surface-side insulating layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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