DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 20-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu(USPGPUB DOCUMENT: 20220310162, hereinafter Wu) in view of Zhang (USPGPUB DOCUMENT: 2021/0375900, hereinafter Zhang) and Zhang (USPGPUB DOCUMENT: 2022/0052062, hereinafter Zhang-062).
Re claim 1 Wu discloses in Fig 16, rotated 180 degrees, a three-dimensional (3D) memory device, comprising: a stack comprising interleaved conductive layers(870) and dielectric layers(656/658); a channel structure(338/337) extending through the stack in a first direction, the channel structure(338/337) comprising a memory film(337) and a semiconductor channel(338) that exceeds the memory film(337) in the first direction, the memory film(337) surrounding the semiconductor channel(338); and a conductor layer(1595)(1595).
Wu does not disclose an adhesive layer disposed on and in contact with the semiconductor channel(338) that exceeds the memory film(337); and a conductor layer(1595) disposed on and in contact with the adhesive layer; and a slit structure extending through and exceeding the stack in the first direction, wherein the adhesive layer is further disposed on and in contact with the slit structure.
Zhang discloses an adhesive layer(123/121 of Zhang) disposed on and in contact with the semiconductor channel(128 of Zhang) that exceeds the memory film(126 of Zhang);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang to the teachings of Wu in order to address the density limitation in planar memory cells [0004, Zhang]. In doing so, a conductor layer(1595) disposed on and in contact with the adhesive layer(123/121 of Zhang).
Wu and Zhang does not disclose a slit structure extending through and exceeding the stack in the first direction, wherein the adhesive layer is further disposed on and in contact with the slit structure.
Zhang-062 disclose in Fig 3D a slit structure(330) extending through and exceeding the stack(314) in the first direction(up/down), wherein the adhesive layer(316) is further disposed on and in contact with the slit structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang-062 to the teachings of Wu in order to improve process technology, circuit design, programming algorithm, and fabrication process [0003, Zhang-062].
Re claim 2 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, wherein the adhesive layer(123/121 of Zhang) is in contact with a sidewall of the semiconductor channel(338) that exceeds the memory film(337).
Re claim 3 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, wherein the adhesive layer(123/121 of Zhang) comprises one of a Ti/TiN layer, a Ta/TaN layer, or a composite layer having a conductive material.
Re claim 4 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, further comprising: a plurality of peripheral contacts each extending in the first direction and being in contact with the adhesive layer(123/121 of Zhang); and a first isolation structure(STI)[0041 of Zhang) extending through the conductor layer(1595) and the adhesive layer(123/121 of Zhang) and extending in a second direction perpendicular to the first direction, the first isolation structure(STI)[0041 of Zhang) comprising a dielectric material, wherein the first isolation structure(STI)[0041 of Zhang) is arranged between two peripheral contacts of the plurality of peripheral contacts to electrically insulate the two peripheral contacts.
Re claim 5 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, wherein:the slit structure[0032 of Zhang] comprises a slit core and an insulating layer surrounding the slit core,the slit core comprising a conductive material; andthe slit core exceeds the insulating layer in the first direction and is in contact with the adhesive layer(123/121 of Zhang).
Re claim 6 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, wherein the stack comprises a first conductive layer(428 of Zhang) in contact with one side of the adhesive layer(123/121 of Zhang) opposite to the conductor layer(1595).
Re claim 7 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 6, wherein the first conductive layer(428 of Zhang) is a polysilicon layer.
Re claim 8 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 6, wherein the first conductive layer(428 of Zhang) is one of the conductive layers(870) of the stack that is closest to the adhesive layer(123/121 of Zhang).
Re claim 9 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, wherein the conductor layer(1595) comprises at least one of aluminum or tungsten.
Re claim 10 Wu and Zhang and Zhang-062 disclose the 3D memory device of claim 1, further comprising: a peripheral contact extending in the first direction and being in contact with the adhesive layer(123/121 of Zhang), the stack comprising a first conductive layer(428 of Zhang) in contact with the adhesive layer(123/121 of Zhang), wherein: the first conductive layer(428 of Zhang) is a polysilicon layer; and the polysilicon layer extends in a third direction perpendicular to the first direction, the peripheral contact and the channel structure(338/337) penetrating the polysilicon layer.
Re claim 20 Wu discloses in Fig 16, rotated 180 degrees, a system, comprising: a three-dimensional (3D) memory device configured to store data[0185] and comprising: a first semiconductor structure comprising: a stack comprising interleaved conductive layers(870) and dielectric layers(656/658); a channel structure(338/337) extending through the stack in a first direction, the channel structure(338/337) comprising a memory film(337) and a semiconductor channel(338) that exceeds the memory film(337) in the first direction, the memory film(337) surrounding the semiconductor channel(338); and a conductor layer(1595);
Wu does not disclose an adhesive layer disposed on and in contact with the semiconductor channel that exceeds the memory film; and a conductor layer(1595) disposed on and in contact with the adhesive layer; and a second semiconductor structure comprising a peripheral circuit bonded with the first semiconductor structure; anda memory controller coupled to the 3D memory device and configured to control the 3D memory device; a slit structure extending through and exceeding the stack in the first direction, wherein the adhesive layer is further disposed on and in contact with the slit structure,
Zhang discloses an adhesive layer(123/121 of Zhang) disposed on and in contact with the semiconductor channel(128 of Zhang) that exceeds the memory film(126 of Zhang); and a second semiconductor structure comprising a peripheral circuit(108 of Zhang) bonded with the first semiconductor structure; anda memory controller(memory circuit)[0041 of Zhang] coupled to the 3D memory device and configured to control the 3D memory device[0041 of Zhang].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang to the teachings of Wu in order to address the density limitation in planar memory cells [0004, Zhang]. In doing so, a conductor layer(1595) disposed on and in contact with the adhesive layer(123/121 of Zhang);
Wu and Zhang does not disclose a slit structure extending through and exceeding the stack in the first direction, wherein the adhesive layer is further disposed on and in contact with the slit structure,
Zhang-062 disclose in Fig 3D a slit structure(330) extending through and exceeding the stack(314) in the first direction(up/down), wherein the adhesive layer(316) is further disposed on and in contact with the slit structure,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Zhang-062 to the teachings of Wu in order to improve process technology, circuit design, programming algorithm, and fabrication process [0003, Zhang-062].
Re claim 21 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the adhesive layer(123/121 of Zhang) is in contact with a sidewall of the semiconductor channel(338) that exceeds the memory film(337).
Re claim 22 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the adhesive layer(123/121 of Zhang) comprises one of a Ti/TiN layer, a Ta/TaN layer, or a composite layer having a conductive material.
Re claim 23 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the 3D memory device further comprises: a plurality of peripheral contacts each extending in the first direction and being in contact with the adhesive layer(123/121 of Zhang); and a first isolation structure(STI)[0041 of Zhang) extending through the conductor layer(1595) and the adhesive layer(123/121 of Zhang) and extending in a second direction perpendicular to the first direction, the first isolation structure(STI)[0041 of Zhang) comprising a dielectric material, wherein the first isolation structure(STI)[0041 of Zhang) is arranged between two peripheral contacts of the plurality of peripheral contacts to electrically insulate the two peripheral contacts.
Re claim 24 Wu and Zhang and Zhang-062 disclose the system of claim 20, the slit structure[0032 of Zhang] comprises a slit core and an insulating layer surrounding the slit core,the slit core comprising a conductive material; andthe slit core exceeds the insulating layer in the first direction and is in contact with the adhesive layer(123/121 of Zhang).
Re claim 25 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the stack comprises a first conductive layer(428 of Zhang) in contact with one side of the adhesive layer(123/121 of Zhang) opposite to the conductor layer(1595).
Re claim 26 Wu and Zhang and Zhang-062 disclose the system of claim 25, wherein the first conductive layer(428 of Zhang) is a polysilicon layer.
Re claim 27 Wu and Zhang and Zhang-062 disclose the system of claim 25, wherein the first conductive layer(428 of Zhang) is one of the conductive layers(870) of the stack that is closest to the adhesive layer(123/121 of Zhang).
Re claim 28 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the conductor layer(1595) comprises at least one of aluminum or tungsten.
Re claim 29 Wu and Zhang and Zhang-062 disclose the system of claim 20, wherein the 3D memory device further comprises: a peripheral contact extending in the first direction and being in contact with the adhesive layer(123/121 of Zhang), the stack comprising a first conductive layer(428 of Zhang) in contact with the adhesive layer(123/121 of Zhang), wherein: the first conductive layer(428 of Zhang) is a polysilicon layer; and the polysilicon layer extends in a third direction perpendicular to the first direction, the peripheral contact and the channel structure(338/337) penetrating the polysilicon layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 20-29 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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