Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DRAM ARRAY WITH VERTICALLY STACKED CAPACITOR STRUCTURE.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1-2,4,6-9,12,18-19 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 2012/0248520 (Hiroyuki).
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Regarding claim 1, Hiroyuki shows (Fig. 1,2,4) a semiconductor device, comprising:
a stack structure (10, para 35) comprising first conductive layers (12b, para 36) and second conductive layers (11, para 36) alternately stacked along a vertical direction;
a conductive wall (12a, para 36) vertically extending through the stack structure and in contact with the first conductive layers but isolated from the second conductive layers; and
conductive vias (14, para 38) each vertically extending through the stack structure and electrically connected with a corresponding one of the second conductive layers but electrically isolated from the first conductive layers and other second conductive layers in the stack structure (para 32).
Regarding claim 2, Hiroyuki shows (Fig. 1,2,4) further comprising:
isolation structures (15, para 39) between the conductive vias (14, para 38) and the other second conductive layers (11, para 36) to isolate the conductive vias and the other second conductive layers; and
conductive connection structures (15a, para 39) each between one of the conductive vias and the corresponding one of the second conductive layers to connect the one of the conductive vias to the corresponding one of the second conductive layers.
Regarding claim 4, Hiroyuki shows (Fig. 1,2,4) each of the isolation structures (15, para 39) and the conductive connection structures (15a, para 39) has a ring structure laterally surrounding a corresponding one of the conductive vias (14, para 38).
Regarding claim 6, Hiroyuki shows (Fig. 1,2,4) a dielectric layer (13, para 35) comprising:
horizontal portions between adjacent first conductive layers (12b, para 36) and second conductive layers (11, para 36);
first vertical portions between the conductive wall (12a, para 36) and the second conductive layers; and
second vertical portions between the conductive vias (14, para 38) and the first conductive layers.
Regarding claim 7, Hiroyuki shows (Fig. 1,2,4) the dielectric layer (13, para 37) is in contact with side surfaces of the conductive wall (12a) and the conductive vias (14, para 38), and horizontal surfaces of the first conductive layers and second conductive layers.
Regarding claim 8, Hiroyuki shows (Fig. 1,2,4) further comprising:
an array of transistors (T1, T2, para 19) coupled with the conductive vias (14, para 38), respectively, wherein the transistors are vertical gate transistors each comprising a channel structure extending along a vertical direction and a gate structure at a lateral side of the channel structure (para 43).
Regarding claim 9, Hiroyuki shows (Fig. 1,2,4) further comprising:
an insulating layer (4 or 5, para 23) between the stack structure (10) and the array of transistors (T1, T2, para 19), wherein each conductive via extends through the insulating layer to couple with a corresponding one of the array of transistors.
Regarding claim 12, Hiroyuki shows (Fig. 1-2,4) a memory device (para 2), comprising:
a capacitor stack structure (10, para 35) comprising:
first electrode plates (12b, para 36) and second electrode plates (11, para 36) alternatively stacked along a vertical direction, a common electrode (12a, para 36) vertically extending through the capacitor stack structure and in contact with the first electrode plates, and select electrodes (14, para 38) each extending through the capacitor stack structure and in contact with a corresponding one of the second electrode plates; and
an array of transistors (T1, T2, para 19) each coupled with a corresponding one of the select electrodes.
Regarding claim 18, Hiroyuki shows (Fig. 1-2,4) an insulating layer (4 or 5) between the capacitor stack structure (10) and the array of transistors (T1,T2), wherein the select electrodes extend through the insulating layer.
Regarding claim 19, Hiroyuki shows (Fig. 1-2,4) the transistors are two-dimensional transistors or vertical gate transistors (para 43).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 3,13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiroyuki, as applied to claim 1 or 12 above, further in view of US 20220045094 A1 (Lee).
Regarding claim 3, Hiroyuki shows the isolation structures and the conductive connection structures.
Hiroyuki does not show the isolation structures comprise silicon oxide; and the conductive connection structures comprise a metal silicide material.
Lee shows (Fig. 20A) the isolation structures (420) comprise silicon oxide (para 45); and
the conductive connection structures (122) comprise a metal silicide material (para 27).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lee, with materials for isolation structures and conductive connection structures, to the invention of Hiroyuki.
The motivation to do so is that the selection of an art recognized materials of Lee is suitable for the intended use of Hiroyuki (MPEP §2144.07).
Regarding claim 13, Hiroyuki shows a first electrode plates (12b, para 36), second electrode plates (11, para 36), the common electrode (12a, para 36), and the select electrodes (14, para 38).
Hiroyuki does not show a high-K layer between adjacent first electrode plates and second electrode plates, between the first electrode plates and the common electrode, and between the second electrode plates and the select electrodes.
Lee shows (Fig. 13A) a high-K layer (420, para 61) as capacitor dielectric.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lee, with capacitor dielectric, to the invention of Hiroyuki.
The motivation to do so is that the selection of an art recognized capacitor dielectric of Lee is suitable for the intended use of Hiroyuki (MPEP §2144.07).
Allowable Subject Matter
Claims 5,10-11,14-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the second conductive layers and the conductive vias comprise a second conductive material different from the first conductive material”.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “first thickness of the first conductive layers is different from a second thickness of the second conductive layers”.
Regarding claim 11, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the conductive wall extends laterally along a second direction to cut off the slit structure”.
Regarding claim 14, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “isolation structures between the one of the select electrodes and other second electrode plates different from the corresponding one of the second electrode plates”.
Regarding claim 17, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the second electrode plates and the select electrodes comprise a second conductive material different from the first conductive material”.
Regarding claim 20, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the common electrode extends laterally along a second direction to cut off the slit structure”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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