Prosecution Insights
Last updated: July 17, 2026
Application No. 18/435,865

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Feb 07, 2024
Priority
Sep 06, 2023 — JP 2023-144353
Examiner
BRECHT, CHARLES MATTHEW
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
21 currently pending
Career history
17
Total Applications
across all art units

Statute-Specific Performance

§103
98.2%
+58.2% vs TC avg
§102
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I (Claims 1-6) in the reply filed on June 3, 2026 is acknowledged. Claims 7-20 have been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanna (JP-2007165371, hereafter Kanna). Regarding claim 1, Kanna discloses a semiconductor device comprising: a semiconductor element (20, Fig. 6) having a first face (20 top), a second face (25, par. 0013) located on an opposite side to the first face, and a side face (20 side) located between the first face and the second face; a first electrode layer (20 top) provided on the first face of the semiconductor element; and a second electrode layer (26, Fig. 6, par. 0014) provided on the second face of the semiconductor element, wherein an outer edge portion on the second face is more rounded compared to an outer edge portion on the first face, and a thickness of the second electrode layer gradually decreases as the second electrode layer extends closer to the side face (Fig. 6). Regarding claim 2, Kanna discloses a device wherein the second electrode layer (26) coats the outer edge portion on the second face (Fig. 6). Regarding claim 3, Kanna discloses a device wherein in a plane parallel to the first face (20 top, Fig. 6), the second electrode layer (26) does not extend outward from the side face (Fig. 6). Regarding claim 4, Kanna discloses a device wherein in a plane parallel to the first face (20 top, Fig. 6), the second electrode layer (26) does not extend outward from the side face (Fig. 6). Regarding claim 5, Kanna discloses a device wherein in the outer edge portion on the second face (25, Fig. 6), the second electrode layer (26) is curved from the second face along the side face (20 side) toward the first face (20 top) (Fig. 6). Regarding claim 6, Kanna discloses a device wherein in the outer edge portion on the second face (25), the second electrode layer (26) is curved from the second face along the side face (20 side) toward the first face (20 top) (Fig. 6). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tsuma (20230154987), pertaining to all claims; Kurosawa (20040130004), pertaining to claim 1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./ Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Feb 07, 2024
Application Filed
Jul 06, 2026
Non-Final Rejection mailed — §102 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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