2DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 26-29 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Claim 26 is independent and comprises distinguished limitations of “a calibration circuit configured to delay a first signal, according to an address of the one of the plurality of weights, to generate the pre-charge signal”.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 26-29 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 21, and 22 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim et al. (US Pub. 2024/0211210).
Regarding claims 1 and 21, Fig. 1 of Kim discloses a memory device, comprising:
a memory array [110] configured to store a plurality of weights [paragraph 0045];
a pre-charging circuit [140] coupled to the memory array [110] through a plurality of data lines [BL, paragraph 0048], and configured to charge, in response to a pre-charge signal (EN_PRE[n]), the data line in the plurality of data lines to a first read voltage [as discloses in paragraph 0048, during reading operation, bit lines are precharged to a voltage. Since the voltage is during a reading operation, it can be considered a read voltage] for a first duration [between 602 and 603 in Fig. 6] in a read operation to a first weight in the plurality of weights; and
a calibration circuit [120] configured to generate the pre-charge signal (EN_PRE[n]) according to an address of the first in the plurality of weights [since the precharged signal is generated to precharge a particular bitline for a selected rows of plurality of rows, it is inherently or at least obvious generated according an address signal (can be row or column address).
Regarding claim 22, Fig. 1 of Kim discloses wherein the calibration circuit [120] is further configured to generate, according to the address [one of the address for one of the row in memory 110] of the first weight in the plurality of weights [paragraph 0048], the pre-charge signal having a first pulse width [between 602 and 603] in the read operation to the first weight, the first weight stored in a first portion of the memory array.
Allowable Subject Matter
Claims 2-11 and 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2-5, the prior art does not teach or suggest either alone or in combination wherein the calibration circuit is further configured to generate, according to an address of a first weight in the plurality of weights, the pre-charge signal having a first pulse width in the read operation to the first weight, the first weight stored in a first portion of the memory array, wherein the calibration circuit is further configured to generate, according to an address of a second weight in the plurality of weights, the pre-charge signal having a second pulse width in the read operation to the second weight, the second weight stored in a second portion, different from the first portion, of the memory array, wherein the first pulse width and the second pulse width are different from each other.
Regarding claims 6-8, the prior art does not teach or suggest either alone or combination wherein in the read operation to a first weight stored in a first portion of the memory array, the pre-charge circuit charges the at least one data line by the read voltage having a first voltage value, and in the read operation to a second weight stored in a second portion of the memory array, the pre-charge circuit charges the at least one data line by the read voltage having a second voltage value smaller than the first voltage value.
Regarding claims 9-11, the prior art does not teach or suggest either alone or in combination wherein the calibration circuit comprises: a delay chain configured to generate, in response to a first signal, a plurality of delay signals; a first multiplexer circuit configured output, in response to a selection signal associated with the address, one of the plurality of delay signals as a second signal; and a logic circuit configured to generate the pre-charge signal in response to the first signal and the second signal.
Regarding claims 23-25, the prior art does not teach or suggest either alone or in combination wherein the calibration circuit is further configured to generate, according to an address of a second weight in the plurality of weights, the pre-charge signal having a second pulse width in the read operation to the second weight, the second weight stored in a second portion, different from the first portion, of the memory array, wherein the first pulse width is larger than the second pulse width, wherein the pre-charging circuit is further configured to charge, in response to the pre-charge signal, the data line in the plurality of data lines to a second read voltage for a second duration in the read operation to the second weight.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825