Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention I in the reply filed on 6/17/2026 is acknowledged.
Claims 8-21 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/17/2026.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2023-0139013 filed on 10/17/2023. The foreign application is not in English. The certified copy of the foreign priority application KR 10-2023-0139013 has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 10-2023-0139013 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "wherein at least one second contact plug is connected to each one of the second contact gates" in lines 10-11. There is insufficient antecedent basis for this limitation in the claim.
NOTE: Examiner is interpreting this to read “wherein at least one second contact plug is connected to each one of the second gate lines.”
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20180247953), hereinafter referred to as Lee 2018 and Hua et al. (US Pub. 20200127003), hereinafter referred to as Hua.
Regarding claim 1, Lee 2018 teaches a semiconductor device comprising: a first gate structure (Lee 2018, ST3, Fig. 4, para. 58) including stacked first gate lines (Lee 2018, CS, Fig. 4, para. 58); first contact plugs (Lee 2018, 193A, Fig. 4, para. 41) extending through the first gate structure, the first contact plugs being connected to the first gate lines, respectively (Lee 2018, para. 66), wherein at least one first contact plug is connected to each one of the first gate lines (Lee 2018, Fig. 4); a second gate structure (Lee 2018, ST3, Fig. 4, para. 58, NOTE: Fig. 3A shows two structures separated by slit SI, therefore duplicate components have the same reference numbers henceforth) including stacked second gate lines (Lee 2018, CS, Fig. 4, para. 58); second contact plugs extending through the second gate structure (Lee 2018, 193A, Fig. 4, para. 41), the second contact plugs being connected to the second gate lines, respectively (Lee 2018, para. 66), wherein at least one second contact plug is connected to each one of the second gate lines (Lee 2018, Fig. 4); and a slit structure (Lee 2018, SI, Fig. 3A, para. 40) located between the first gate structure and the second gate structure electrically isolating the first gate structure from the second gate structure.
Lee 2018 does not teach the slit structure including a lower sidewall having a wave shape and an upper sidewall having a straight line shape.
However, Hua teaches a three dimensional memory device with a slit structure wherein the lower sidewall has a wave-like appearance (Hua, 546, Fig. 6B (lower part), para. 73, ) and the upper sidewall has a straight line shape in the direction of travel (Hua, 546, Fig. 6B upper part, para. 73).
Therefore, it would have been obvious to one having ordinary skill in the art to have combined the device of Lee 2018 with the slit configuration of Hua in order to reduce fabrication steps and costs (Hu, para. 57),
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Regarding claim 2, modified Lee 2018 teaches the semiconductor device of claim 1, wherein the slit structure extends in a first direction (Lee 2018, Fig. 3A),
and wherein the first gate structure and the second gate structure are adjacent to each other in a second direction intersecting the first direction (Lee 2018, Fig. 3A).
Regarding claim 3, modified Lee 2018 teaches the semiconductor device of claim 2, wherein the lower sidewall has a shape in which concave portions and convex portions are alternately arranged along the first direction (Hua, 546, Fig. 6B, lower part, para. 73).
Regarding claim 4, modified Lee 2018 teaches the semiconductor device of claim 1, wherein the first contact plugs extend into the first gate structure at different depths (Lee 2018, 193A, Fig. 4),
Regarding claim 5, modified Lee 2018 teaches the semiconductor device of claim 1, wherein the second contact plugs extend into the second gate structure at different depths (Lee 2018, 193A, Fig. 4).
Regarding claim 7, modified Lee 2018 teaches the semiconductor device of claim 1, further comprising: a first channel structure extending through the first gate structure (Lee 2018, CPL, Fig. 4, para. 40);
and a second channel structure extending through the second gate structure (Lee 2018, CPL, Fig. 4, para. 40).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee 2018 and Hua as applied to claim 1 above, and further in view of Lee (US Pub.20150349109), hereinafter known as Lee 2015.
Regarding claim 6, modified Lee 2018 teaches the semiconductor device of claim 1, but does not teach further comprising: first insulating spacers surrounding sidewalls of the first contact plugs, respectively; and second insulating spacers surrounding sidewalls of the second contact plugs, respectively. Lee 2018 does teach that the contact plugs penetrate through a planarization insulating layer (Lee 2018, 169, Fig. 4, para. 63).
However, Lee 2015 teaches a semiconductor device wherein the contact plugs (Lee 2015, CT[12]-CT[mn], Fig. 2A, para. 34) are covered by a spacer insulating layer (Lee, 2015, 181, Fig. 4, para. 34). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Lee 2018 and Hua with the spacer of Lee 2015 in order to allow the contact plugs to prevent protrusions forming except on the target layer (Lee, 2015, para. 34). This configuration also allows the stepped structure to be removed, allowing the semiconductor to be reduced in size (Lee 2015, para. 38).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fantini et al. (US Pub. 20200203429) teaches an insulating trench with a wavelike profile.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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