Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to the newly amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ding (US 20220336326 A1).
PNG
media_image1.png
528
770
media_image1.png
Greyscale
CLAIM 1. Ding discloses a semiconductor device, comprising: an upper line including an opening (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); a lower line positioned below the upper line and overlapping with the opening in a first direction (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); an auxiliary line positioned below the lower line and overlapping with the opening in the first direction, wherein the auxiliary line contacts a lower surface of the lower line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.)
an upper plug connecting the upper line and the lower line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); and
a lower pluq positioned below the lower line and spaced apart from the auxiliary line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); wherein the upper pluq is electrically connected to the lower pluq through the auxiliary line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.).
PNG
media_image2.png
440
756
media_image2.png
Greyscale
PNG
media_image3.png
754
697
media_image3.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding (US 20220336326 A1) in view of Park et al. (US 20220310506 A1).
Ding discloses a semiconductor device, comprising: an upper line including an opening (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); a lower line positioned below the upper line and overlapping with the opening in a first direction (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); an auxiliary line positioned below the lower line and overlapping with the opening in the first direction, wherein the auxiliary line contacts a lower surface of the lower line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.)
an upper plug connecting the upper line and the lower line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); and
a lower pluq positioned below the lower line and spaced apart from the auxiliary line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.); wherein the upper pluq is electrically connected to the lower pluq through the auxiliary line (Ding Fig. 1 – See below mapping of Applicant’s claimed elements to the analogous structural feature found in Ding Fig. 1.).
PNG
media_image2.png
440
756
media_image2.png
Greyscale
PNG
media_image4.png
666
826
media_image4.png
Greyscale
While, Ding discloses an analogous structure meeting the BRI of the claimed structure that may allow for a via line [AL] to be considered a “auxiliary layer”, it would be also an option to form the lower metal layer of two distinct metal layers, thus meeting the more limited interpretation as understood from the written description and figure, albeit not necessarily required by the claim language.
Park et al. demonstrates a insertion metal layer 310 [e.g. lower metal layer] may further be located over a layer 110 [e.g. auxiliary layer]. Park teaches the conductive insertion pattern 310 is stacked on the lower wiring layer 110 to reduce contact resistance and/or provide a wider “landing pad” area that facilitates the successful alignment of the upper via structures.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the metal level of Ding of metal level of Park to include a insertion/auxiliary layer, since applying a known technique (providing a second metal layer) to a known device ready for improvement to yield predictable results (reduce resistance, increased contact area, etc.) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 2. Ding in view of Park discloses a semiconductor device of claim 1, wherein the auxiliary line contacts a portion of the lower surface of the lower line (Fig. 1).
CLAIM 3. Ding in view of Park discloses a semiconductor device of claim 1, wherein a planar area of the auxiliary line is greater than a planar area of the opening in the upper line (Ding as modified by Park, the auxiliary layer would be approximately similar dimensions and length, thereby having the greater planar area than the opening.).
CLAIM 4. Ding in view of Park discloses a semiconductor device of claim 1, wherein a width of the auxiliary line in a second direction (e.g. horizontal viewing direction) intersecting the first direction is greater than a width of the opening in the upper line in the second direction (Ding as modified by Park, the auxiliary layer would be approximately similar dimensions and length, thereby having the greater width than the opening.).
CLAIM 5. Ding in view of Park discloses a semiconductor device of claim 1, wherein the upper plug protrudes downwards from the upper line and contacts the lower line; wherein the lower plug protrudes downwards from the lower line and contacts a target plug (Fig. 1).
CLAIM 6. Ding in view of Park discloses a semiconductor device of claim 1, wherein the upper plug and the lower plug are located on opposite sides of the auxiliary line in a second direction intersecting the first direction (Fig. 1).
CLAIM 7. Ding in view of Park discloses a semiconductor device of claim 1, wherein the auxiliary line is located between the upper plug and the lower plug in the second direction (Fig. 1).
CLAIM 8. Ding in view of Park discloses a semiconductor device of claim 1, wherein the auxiliary line and the lower line, together, form a current path between the upper plug and the lower plug (Fig. 1- This limitation does not provide any further structural distinction.).
CLAIM 9. Ding in view of Park discloses a semiconductor device of claim 1, wherein the lower line and the auxiliary line include the same material (Fig. 1- The conductive lines are disclosed to be formed of the same group of selectable materials. ¶24).
CLAIM 10. Ding in view of Park discloses a semiconductor device of claim 9, wherein the lower line and the auxiliary line include copper (Cu) (Fig. 1- The conductive lines are disclose to be formed of the same group of selectable materials. ¶29).
CLAIM 11. Ding in view of Park discloses a semiconductor device of claim 1, further comprising a stacked structure located under the upper line, the lower line, and the auxiliary line, wherein the stacked structure includes first material layers and second material layers, which are alternately stacked (The claim does not clearly define what is to be considered a stacked structure or number of layers. The overly broad ambiguous language may describe simple build up layers for metallization. Fig. 10 further depicts at least one insulating layer and metal layer below the identified structures meeting the broad scope of the claim under BRI.).
CLAIM 12. Ding in view of Park in view of Zhang discloses a semiconductor device of claim 11, the device structure further comprising a target plug penetrating the stacked structure (Fig. 1 – e.g. metallization plugs/lines located below the lower plug of Ding.).
CLAIM 13. Ding in view of Park discloses a semiconductor device of claim 12, wherein the target plug is electrically coupled to the upper line through the lower line and the auxiliary line (Fig. 1).
CLAIM 14. Ding in view of Park discloses a semiconductor device of claim 12, further comprising a peripheral circuit (e.g. 130) located under the stacked structure (Ding Fig. 1).
CLAIM 15. Ding in view of Park discloses a semiconductor device of claim 14, wherein the target plug is electrically coupled to the peripheral circuit (Ding fig. 1.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/10/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
Prosecution Insights