DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/19/2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments have overcome the 112(b) rejections of claims 5 and 6 as previously set forth in the Non-Final Office Action mailed on 05/29/2026.
The receipt of requested drawings and updated specification is acknowledged.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 09/24/2021. It is noted, however, that applicant has not filed a certified copy of the CN-202111122149.3 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitations: “wherein the active region comprises a plurality of active region groups sequentially disposed along the second direction” and “the semiconductor device further comprises an inactive region surrounding the active region”. These limitations do not require the presence of inactive region between the active region groups or between the first and second active regions as shown in Fig.1 or 5, where the first source of drain connection lines must be located according to the other limitations of the claim. Furthermore, the limitation “each of the plurality of first source connection line segments and each of the plurality of first drain connection line segments are located in the inactive region on two sides of one of the first active region or the second active region in a same active region group” does not require that the two sides are opposite sides as shown in Fig.1 or 5 (there is no requirement that the first and second active regions are rectangles).
For the purpose of examination, claim 7 will be interpreted as: The semiconductor device according to claim 3, wherein the active region comprises a plurality of active region groups sequentially disposed along the second direction, and each of the plurality of active region groups comprises a first active region and a second active region disposed along the second direction; the semiconductor device further comprises an inactive region surrounding each of the first and second active region of each group; along the second direction, each of the plurality of first source connection line segments and each of the plurality of first drain connection line segments are located in the inactive region on two opposite sides of one of the first active region or the second active region in a same active region group; and along the first direction, the second source connection line segment and the second drain connection line segment are located in the inactive region on two opposite sides of the plurality of active region groups.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al., (United States Patent Application Publication Number, US 2019/0189764 A1) hereinafter referenced as Lin_764.
Regarding claim 1, Lin_764 teaches a semiconductor device, comprising an active region (Fig.2A, element #120), and the semiconductor device further comprising: a substrate (Fig.2B, element #110); an epitaxial structure located on a side of the substrate (Fig.2B, elements #123 and #124, paragraph [0034], rows 5-8), and a two-dimensional electron gas being formed in the epitaxial structure located in the active region(paragraph [0034], rows 15-21); an electrode structure located on a side, away from the substrate, of the epitaxial structure and located in the active region, and the electrode structure comprising a plurality of ohmic contact electrodes (Fig.2B, elements #150, #160 and #130); a first dielectric layer located on a side, away from the substrate of the electrode structure, and the electrode structure being covered by the first dielectric layer (Fig.4B, element #180); an electrode connection line located on a side, away from the substrate, of the first dielectric layer the electrode connection line comprising an ohmic contact electrode connection Line, and the ohmic contact electrode connection Line being electrically connected to the plurality of ohmic contact electrodes (Fig.5A and 5B, elements #210, #220 and #240); a second dielectric layer located on a side, away from the substrate, of the electrode connection line, and the electrode connection line being covered by the second dielectric layer (Fig.6B, elements #250); and an electrode bonding pad located on a side, away from the substrate, of the second dielectric layer and electrically connected to the electrode connection line by a via in the second dielectric layer (Fig.7A, elements #260 and #270 are connected by via #257 and #259), the electrode bonding pad comprising an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line (Fig.7B, elements #260 and #270 are connected to elements #150 and #140), and at least a part of the ohmic contact electrode bonding pad being located in the active region, wherein the at least a part of the ohmic contact electrode bonding pad is disposed above the two-dimensional electron gas located in the active region (Fig.7A elements #260 and #270 are located on top of the entire active area, and therefor overlap the 2DEG), such that a parasitic capacitance between the at least a part of the ohmic contact electrode bonding pad and the substrate is shielded by the two-dimensional electron gas ( Fig.7B and 7C, the 2DEG is directly interposed between the substrate and parts of the ohmic contact electrode bonding pad, and therefore the parasitic capacitance between the pad and the substrate is shielded by the 2DEG in these overlap regions).
Regarding claim 2, Lin_764 teaches the semiconductor device according to claim 1 as set forth in the anticipation rejection. Lin_764 further teaches the semiconductor device according to claim 1, wherein the plurality of ohmic contact electrodes comprise at least one source electrode and at least one drain electrode (Fig.2B, element #150 and #160 respectively); the ohmic contact electrode connection line comprises a source connection line and a drain connection line (Fig.5B, element #220 and #240 respectively), the source connection line is electrically connected to the at least one source electrode (Fig.5B, element #220 is electrically connected to element #150), and the drain connection line is electrically connected to the at least one drain electrode (Fig.5B, element #240 is electrically connected to element #160); the ohmic contact electrode bonding pad comprises a source bonding pad and a drain bonding pad (Fig.7A, element #260 and #270 respectively), the source bonding pad is electrically connected to the source connection line (Fig.7B, element #260 is electrically connected to element #220), and the drain bonding pad is electrically connected to the drain connection line (Fig.7B, element #270 is electrically connected to element #240); and on a plane where the substrate is located, a vertical projection of the source connection line is located outside a vertical projection of the drain connection line (Fig.5A the vertical projection of the left and right side elements #220 is outside a vertical projection of elements #240).
Regarding claim 20, Lin_764 teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (Fig.2B, element #110); preparing an epitaxial structure on a side of the substrate (Fig.2B, elements #123 and #124, paragraph [0034], rows 5-8), and a two-dimensional electron gas being formed in the epitaxial structure located in an active region of the semiconductor device (paragraph [0034], rows 15-21); preparing an electrode structure on a side, away from the substrate, of the epitaxial structure and in the active region, and the electrode structure comprising a plurality of ohmic contact electrodes (Fig.2B, elements #150, #160 and #130); preparing a first dielectric layer on a side, away from the substrate, of the electrode structure, and the electrode structure being covered by the first dielectric layer (Fig.4B, element #180); preparing an electrode connection line on a side, away from the substrate, of the first dielectric layer, the electrode connection line comprising an ohmic contact electrode connection line, and the ohmic contact electrode connection line being electrically connected to the plurality of ohmic contact electrodes(Fig.5A and 5B, elements #210, #220 and #240); preparing a second dielectric layer on a side, away from the substrate, of the electrode connection line, and the electrode connection line being covered by the second dielectric layer (Fig.6B, elements #250); and preparing an electrode bonding pad on a side, away from the substrate, of the electrode connection line and electrically connected to the electrode connection line by a via in the second dielectric layer (Fig.7A, elements #260 and #270 are connected by via #257 and #259), the electrode bonding pad comprising an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line (Fig.7B, elements #260 and #270 are connected to elements #150 and #140),, and at least a part of the ohmic contact electrode bonding pad being located in the active region, wherein the at least a part of the ohmic contact electrode bonding pad is disposed above the two-dimensional electron gas located in the active region (Fig.7A elements #260 and #270 are located on top of the entire active area, and therefor overlap the 2DEG), such that a parasitic capacitance between the at least a part of the ohmic contact electrode bonding pad and the substrate is shielded by the two-dimensional electron gas ( Fig.7B and 7C, the 2DEG is directly interposed between the substrate and parts of the ohmic contact electrode bonding pad, and therefore the parasitic capacitance between the pad and the substrate is shielded by the 2DEG in these overlap regions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective fiLin_843g date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., (United States Patent Number, US 9,508,843 B2) hereinafter referenced as Lin_843 in view of Mizan et al., (United States Patent Number US 10,218,346 B1) hereinafter referenced as Mizan.
Regarding claim 1, Lin_843 teaches a semiconductor device, comprising an active region (Fig.2, element #102), and the semiconductor device further comprising: a substrate (Fig.7B, element #300); an structure located on a side of the substrate (Fig.7B, element #110, located on top side of element #300), and a two-dimensional electron gas being formed in the structure located in the active region (column 7, rows 58-65).
Lin_843 teaches the structure located on a side of the substrate comprises gallium nitride compounds as part of 2DEG transistor channel (column 7, rows 61-67). Lin_843 does not teach the structure is an epitaxial structure. Mizan teaches an epitaxial structure comprising gallium nitride as part of a 2DEG transistor channel (column 3, rows 35-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizan and disclose the structure is an epitaxial structure. Growing structures using epitaxy minimizes the defects that may occur during growth or deposition as compared to other growing or deposition methods, and results in high quality devices.
Lin_843 further teaches an electrode structure (Fig.7B, formed by elements #120, #130 and #140) located on a side, away from the substrate, of the epitaxial structure and located in the active region and the electrode structure comprising a plurality of ohmic contact electrodes (Fig.7B, formed by elements #120 and #130, column 7, rows 1-3 and rows 15-17), a first dielectric layer located on a side, away from the substrate, of the electrode structure and the electrode structure being covered by the first dielectric layer (Fig.4, element #150); an electrode connection line located on a side, away from the substrate, of the first dielectric layer the electrode connection line comprising an ohmic contact electrode connection line (Fig.7B formed by elements #160, #170 and #180), and the ohmic contact electrode connection line being electrically connected to the plurality of ohmic contact electrodes (Fig.7B, elements #160 and #170 are electrically connected to elements #120 and #130 through vias); a second dielectric layer located on a side, away from the substrate, of the electrode connection line, and the electrode connection line being covered by the second dielectric layer (Fig.7B, element #230); and an electrode bonding pad located on a side, away from the substrate, of the second dielectric layer (Fig.6, formed by elements #244, #242, #254 and #252), and electrically connected to the electrode connection line by a via in the second dielectric layer (Fig.7B, elements #245 and Fig.7C, elements #255), the electrode bonding pad comprising an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line (Fig.7B,elements #242 and #160 are electrically connected, Fig.7C, elements #252 and #170 are electrically connected)
and at least a part of the ohmic contact electrode bonding pad being located in the active region (Fig.6, elements #242, #244, #252 and #254 are located in the active region #102),
wherein the at least a part of the ohmic contact electrode bonding pad is disposed above the two-dimensional electron gas located in the active region (Fig.7B and Fig.7C, which are cross-sections of Fig.6 along lines 7B and 7C respectively, show elements #242 and #252 above the structure #110, the 2DEG is located at the interface between layers #112 and #114, column 7, row 67 and column 8, rows 1-2; Fig.6, elements #242 and #252 are inside the active region, element #102), such that a parasitic capacitance between the at least a part of the ohmic contact electrode bonding pad and the substrate is shielded by the two-dimensional electron gas (Fig.7B and 7C, the 2DEG is present at the interface between layers #112 and #114, and is directly interposed between the substrate and the ohmic contact electrode bonding pad in some of the overlap regions, therefore the parasitic capacitance between the two layers is shielded by the 2DEG in these overlap regions).
Regarding claim 20, Lin_843 teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (Fig.7B, element #300); preparing an structure on a side of the substrate (Fig.7B, element #110, located on top side of element #300), and a two-dimensional electron gas being formed in the structure located in an active region of the semiconductor device (Fig.2, active region #102, column 7, rows 58-65).
Lin_843 teaches the structure located on a side of the substrate comprises gallium nitride compounds as part of 2DEG transistor channel (column 7, rows 61-67). Lin_843 does not teach the structure is an epitaxial structure. Mizan teaches an epitaxial structure comprising gallium nitride as part of a 2DEG transistor channel (column 3, rows 35-45). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Mizan and disclose the structure is an epitaxial structure. Growing structures using epitaxy minimizes the defects that may occur during growth or deposition as compared to other growing or deposition methods, and results in high quality devices.
Lin_843 further teaches preparing an electrode structure on a side, away from the substrate, of the epitaxial structure and in the active region (Fig.7B, formed by elements #120, #130 and #140), and the electrode structure comprising a plurality of ohmic contact electrodes (Fig.7B, formed by elements #120 and #130, column 7, rows 1-3 and rows 15-17); preparing a first dielectric layer on a side, away from the substrate, of the electrode structure, and the electrode structure being covered by the first dielectric layer (Fig.4, element #150); preparing an electrode connection line on a side, away from the substrate, of the first dielectric layer, the electrode connection line comprising an ohmic contact electrode connection line (Fig.7B formed by elements #160, #170 and #180), and the ohmic contact electrode connection line being electrically connected to the plurality of ohmic contact electrodes (Fig.7B, elements #160 and #170 are electrically connected to elements #120 and #130 through vias); preparing a second dielectric layer on a side, away from the substrate, of the electrode connection line, and the electrode connection line being covered by the second dielectric layer (Fig.7B, element #230); and preparing an electrode bonding pad on a side, away from the substrate, of the electrode connection line (Fig.6, formed by elements #244, #242, #254 and #252), and electrically connected to the electrode connection line by a via in the second dielectric layer (Fig.7B, elements #245 and Fig.7C, elements #255), the electrode bonding pad comprising an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line (Fig.7B,elements #242 and #160 are electrically connected, Fig.7C, elements #252 and #170 are electrically connected), and at least a part of the ohmic contact electrode bonding pad being located in the active region (Fig.6, elements #242, #244, #252 and #254 are located in the active region #102), wherein the at least a part of the ohmic contact electrode bonding pad is disposed above the two-dimensional electron gas located in the active region, such that a parasitic capacitance between the at least a part of the ohmic contact electrode bonding pad and the substrate is shielded by the two-dimensional electron gas (Fig.7B and 7C, the 2DEG is present at the interface between layers #112 and #114, and is directly interposed between the substrate and the ohmic contact electrode bonding pad in some of the overlap regions, therefore the parasitic capacitance between the two layers is shielded by the 2DEG in these overlap regions).
Claims 1, 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lin_843 et al., (United States Patent Number, US 9,508,843 B2) hereinafter referenced as Lin_843 in view of Mizan et al., (United States Patent Number US 10,218,346 B1) hereinafter referenced as Mizan.
Regarding claim 1, Lin_843 teaches a semiconductor device, comprising an active region (Fig.2, element #102), and the semiconductor device further comprising: a substrate (Fig.7B, element #300); an structure located on a side of the substrate (Fig.7B, element #110, located on top side of element #300), and a two-dimensional electron gas being formed in the structure located in the active region (column 7, rows 58-65).
Lin_843 teaches the structure located on a side of the substrate comprises gallium nitride compounds as part of 2DEG transistor channel (column 7, rows 61-67). Lin_843 does not teach the structure is an epitaxial structure. Mizan teaches an epitaxial structure comprising gallium nitride as part of a 2DEG transistor channel (column 3, rows 35-45). It would have been obvious to one ordinary skilled in the art, before the effective fiLin_843g date of the claimed invention, to incorporate the teachings of Mizan and disclose the structure is an epitaxial structure. Growing structures using epitaxy minimizes the defects that may occur during growth or deposition as compared to other growing or deposition methods, and results in high quality devices.
Lin_843 further teaches an electrode structure (Fig.7B, formed by elements #120, #130 and #140) located on a side, away from the substrate, of the epitaxial structure and located in the active region and the electrode structure comprising a plurality of ohmic contact electrodes (Fig.7B, formed by elements #120 and #130, column 7, rows 1-3 and rows 15-17), a first dielectric layer located on a side, away from the substrate, of the electrode structure and the electrode structure being covered by the first dielectric layer (Fig.4, formed by element #150 labeled in Fig.5, and element #230); an electrode connection line located on a side, away from the substrate, of the first dielectric layer the electrode connection line comprising an ohmic contact electrode connection line (Fig.8 formed by elements #242, #244, #252, #254 and #180), and the ohmic contact electrode connection line being electrically connected to the plurality of ohmic contact electrodes (Fig.7B and 7C, elements #242 and #252 are electrically connected to elements #120 and #130 through vias); a second dielectric layer located on a side, away from the substrate, of the electrode connection line, and the electrode connection line being covered by the second dielectric layer (Fig.9A, element #270); and an electrode bonding pad located on a side, away from the substrate, of the second dielectric layer (Fig.8, formed by elements #280, #290 and #260) and electrically connected to the electrode connection line by a via in the second dielectric layer (Fig.9A, elements #285 and Fig.7C, elements #295), the electrode bonding pad comprising an ohmic contact electrode bonding pad, the ohmic contact electrode bonding pad being electrically connected to the ohmic contact electrode connection line (Fig.9A, elements #280 and #240 are electrically connected, Fig.9C, elements #290 and #250 are electrically connected) and at least a part of the ohmic contact electrode bonding pad being located in the active region (Fig.8, elements #280 and #280 are located on top of and completely cover elements #242 and #252, Fig.6, elements #242 and, #252 are located in the active region #102), wherein the at least a part of the ohmic contact electrode bonding pad is disposed above the two-dimensional electron gas located in the active region (Fig.8, elements #280 and #290 are located on top of and completely cover elements #242 and #252, Fig.7B and Fig.7C, which are cross-sections of Fig.6 along lines 7B and 7C respectively, show elements #242 and #252 above the structure #110, the 2DEG is located at the interface between layers #112 and #114, column 7, row 67 and column 8, rows 1-2; Fig.6, elements #242 and #252 are inside the active region, element #102), such that a parasitic capacitance between the at least a part of the ohmic contact electrode bonding pad and the substrate is shielded by the two-dimensional electron gas (Fig.8, part of elements #280 and #290 overlap with regions between elements #254 and #244, the 2DEG is present at the interface between layers #112 and #114, and located in the regions between elements #120 and #130, which are also regions between elements #254 and #244, see Fig.7A. The 2DEG is directly interposed between the substrate and the ohmic contact electrode bonding pad in the above overlap regions, therefore the parasitic capacitance between the two layers is shielded by the 2DEG in these overlap regions).
Regarding claim 2, the combination of Lin_843 and Mizan teaches the semiconductor device according to claim 1 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 1, wherein the plurality of ohmic contact electrodes comprise at least one source electrode (Fig.7B, element #120, column 7, row 1 and column 8, rows 21-23) and at least one drain electrode (Fig.7B, element #130, column 7, row 15 and column 8, rows 21-23); the ohmic contact electrode connection line comprises a source connection line (Fig.8 formed by elements #242, #244), and a drain connection line (Fig.8 formed by elements #252 and #254), the source connection line is electrically connected to the at least one source electrode (Fig.7B elements #242 is electrically connected to element #120), and the drain connection line is electrically connected to the at least one drain electrode (Fig.7C elements #252 is electrically connected to element #130); the ohmic contact electrode bonding pad comprises a source bonding pad and a drain bonding pad (Fig.8, elements #280 and #290), the source bonding pad is electrically connected to the source connection line (Fig.8, element #280 is connected to element #242 through element #285, which fills via #272), and the drain bonding pad is electrically connected to the drain connection line (Fig.9C, element #290 is connected to element #252 through element #295 which fill via #274); and on a plane where the substrate is located, a vertical projection of the source connection line is located outside a vertical projection of the drain connection line (Fig.8).
Regarding claim 3, the combination of Lin_843 and Mizan teaches the semiconductor device according to claims 1 and 2 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 2, wherein the at least one source electrode comprises a plurality of source electrodes (Fig.7B, element #120, column 7, row 1 and column 8, rows 21-23), the at least one drain electrode comprises a plurality of drain electrodes (Fig.7B, element #130, column 7, row 15 and column 8, rows 21-23), the active region is provided with the plurality of source electrodes and the plurality of drain electrodes (Fig.2, element #102 is provided with elements #120 and #130), the plurality of source electrodes are arranged along a first direction (Fig.7B, elements #120 are arranged under elements #160 which are arranged along the horizontal direction of Fig.6), each of the plurality of source electrodes extends along a second direction (elements #120 extends in the vertical direction of Fig.8 and 6, Fig.9A corresponds to a cross section along the vertical direction of Fig.8 and shows element #120 extending in that direction) the plurality of drain electrodes are arranged along the first direction (Fig.7B, elements #130 are arranged under elements #170 which are arranged along the horizontal direction of Fig.6), each of the plurality of drain electrodes extends along the second direction (elements #130 extends in the vertical direction of Fig.8 and 6, Fig.9B corresponds to a cross section along the vertical direction of Fig.8 and shows element #130 extending in that direction), and the first direction and the second direction intersect and are both parallel to the plane where the substrate is located (Fig.8, the horizontal and vertical directions are in top view); the source connection line comprises a plurality of first source connection line segments (Fig.8, elements #244) and a second source connection line segment (Fig.8, element #242), the plurality of first source connection Line segments are electrically connected to the plurality of source electrodes (Fig.7B, elements #244 are connected to elements #120), and the second source connection line segment is electrically connected to the plurality of first source connection line segments (Fig.8); and the drain connection line comprises a plurality of first drain connection line segments (Fig.8, elements #254) and a second drain connection line segment (Fig.8, elements #252), the plurality of first drain connection line segments are electrically connected to the plurality of drain electrodes (Fig.7B, elements #254 are connected to elements #130), and the second drain connection line segment is electrically connected to the plurality of first drain connection line segments (Fig.8).
Claims 8-11, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over, Lin_843 in view of Mizan and in view of Kaibara et al., (United States Patent Application Publication Number, US 2014/0124867 A1) hereinafter referenced as Kaibara.
Regarding claim 8, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 2, wherein the electrode structure further comprises at least one gate electrode (Fig.7B, element #140); the electrode connection line further comprises a gate connection line (Fig.6, element #180), and the gate connection line is electrically connected to the at least one gate electrode (Fig.7B, element #180 is electrically connected to element #140); and the electrode bonding pad further comprises a gate bonding pad, the gate bonding pad is electrically connected to the gate connection line (Fig.6, element #260).
The combination of Lin_843 and Mizan does not teach and at least a part of the gate bonding pad is located in the active region, wherein the at least a part of the gate bonding pad is disposed above the two-dimensional electron gas located in the active region. Kaibara teaches at least a part of the gate bonding pad is located in the active region, wherein the at least a part of the gate bonding pad is disposed above the two-dimensional electron gas located in the active region. (Fig.1, element #22, a portion of element #22 is disposed on the left side of the drain electrode located on the bottom right corner of the figure, and therefore over a 2DEG channel between this drain electrode and the next source electrode to the right). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Kaibara and disclose at least a part of the gate bonding pad is located in the active region. Having at least a part of the gate bonding pad located in the active region may help reduce the footprint of the device, as compared to having the entire gate bonding pad outside the active region.
Regarding claim 9, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Lin_843, Mixan and Kaibara teaches the semiconductor device of claim 8 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 8, wherein on the plane where the substrate is located, a vertical projection of the gate connection line partially overlaps with the vertical projection of the source connection line (Fig.8, element #180 overlaps with element #242).
Regarding claim 10, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Lin_843, Mixan and Kaibara teaches the semiconductor device of claim 8 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 8, wherein on the plane where the substrate is located, a vertical projection of the gate connection line partially overlaps with the vertical projection of the drain connection line (Fig.8, element #180 overlaps with element #252).
Regarding claim 11, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Lin_843, Mixan and Kaibara teaches the semiconductor device of claim 8 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 8, wherein the at least one source electrode comprises a plurality of source electrodes (Fig.7B, element #120, column 7, row 1 and column 8, rows 21-23), the at least one drain electrode comprises a plurality of drain electrodes (Fig.7B, element #130, column 7, row 15 and column 8, rows 21-23), the at least one gate electrode comprises a plurality of gate electrodes (Fig.7B, element #140, column 8, rows 21-23), the active region is provided with the plurality of source electrodes, the plurality of gate electrodes and the plurality of drain electrodes (Fig.2, element #102 is provided with a plurality of elements #120, #130 and #140, columns 8, rows 14-16 and 21-23), the plurality of source electrodes are arranged along a first direction (Fig.7B, elements #120 are arranged under elements #160 which are arranged along the horizontal direction of Fig.6), each of the plurality of source electrodes extends along a second direction (elements #120 extends in the vertical direction of Fig.8 and 6, Fig.9A corresponds to a cross section along the vertical direction of Fig.8 and shows element #120 extending in that direction), the plurality of gate electrodes are arranged along the first direction (Fig.7B, elements #140 are arranged under elements #180 which are arranged along the horizontal direction of Fig.6), each of the plurality of gate electrodes extends along the second direction (elements #140 extends in the vertical direction of Fig.8 and 6,same as elements #180), the plurality of drain electrodes are arranged along the first direction (Fig.7B, elements #130 are arranged under elements #170 which are arranged along the horizontal direction of Fig.6), each of the plurality of drain electrodes extends along the second direction (elements #130 extends in the vertical direction of Fig.8 and 6, Fig.9B corresponds to a cross section along the vertical direction of Fig.8 and shows element #130 extending in that direction), the gate electrode is located between the source electrode and the drain electrode along the first direction (Fig.7B), and the first direction and the second direction intersect and are both parallel to the plane where the substrate is located (Fig.8, the horizontal and vertical directions are in top view); the source connection line comprises a plurality of first source connection line segments (Fig.8, elements #244) and a second source connection line segment (Fig.8, element #242), the plurality of first source connection line segments are electrically connected to the plurality of source electrodes (Fig.7B, elements #244 are connected to elements #120), and the second source connection line segment is electrically connected to the plurality of first source connection line segments (Fig.8); the gate connection line comprises a plurality of first gate connection line segments (Fig.6, vertical segments of element #180) and a second gate connection line segment (Fig.8, horizontal segment of element #180), the plurality of first gate connection line segments are electrically connected to the plurality of gate electrodes (Fig.7B, element #180 are connected to element #140), and the second gate connection line segment is electrically connected to the plurality of first gate connection line segments (Fig.8); and the drain connection line comprises a plurality of first drain connection line segments (Fig.8, elements #254) and a second drain connection Line segment (Fig.8, elements #252), the plurality of first drain connection line segments are electrically connected to the plurality of drain electrodes (Fig.7B, elements #254 are connected to elements #130), and the second drain connection line segment is electrically connected to the plurality of first drain connection line segments (Fig.8).
Regarding claim 18, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Lin_843, Mixan and Kaibara teaches the semiconductor device of claims 8 and 11 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 11, wherein the source connection line and the drain connection line are disposed in a same layer (Fig.7A, elements #240 and #250 are disposed in the same layer).
Regarding claim 19, the combination of Lin_843 and Mizan teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Lin_843, Mixan and Kaibara teaches the semiconductor device of claims 8, 11 and 18 as set forth in the obviousness rejection. Lin_843 further teaches the semiconductor device according to claim 18, wherein the first dielectric layer comprises a first sub-dielectric layer (Fig.7B, element #150, element #150 is labeled in Fig.5) and a second sub-dielectric layer that are stacked (Fig.7B, element #230), and the first sub-dielectric layer is located on a side, close to the substrate, of the second sub-dielectric layer (Fig.7B, element #150 is located between element #230 and the substrate); and the gate connection line is located on a side, away from the substrate, of the first sub-dielectric layer (Fig.7A, element #180 is located on the top side of element #150), and the source connection line and the drain connection line are located on a side, away from the substrate, of the second sub-dielectric layer (Fig.7A, elements #240 and #250 are located on the top surface of element #230).
Allowable Subject Matter
Claim 4, 5, 6, 12-17 are allowed if written in independent form. Claim 7 is allowed if written in independent form and amended to overcome the 112(b) rejection.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 4 the cited prior art does not teach or fairly suggests, along with other
claimed features: “along the second direction, each of the plurality of first source connection line segments and each of the plurality of first drain connection line segments are located on two opposite sides of one of the first active region or the second active region in a same active region group; and along the first direction, the second source connection line segment and the second drain connection line segment are located on two opposite sides of the plurality of active region”.
Regarding claim 5, the cited prior art does not teach or fairly suggests, along with other
claimed features: “each of the plurality of first source connection line segments is located between the first active region and the second active region in a same active region group”.
Regarding claim 6, the cited prior art does not teach or fairly suggests, along with other
claimed features: “each of the plurality of first drain connection line segments is located between the first active region and the second active region in a same active region group”.
Regarding claim 7, the cited prior art does not teach or fairly suggests, along with other
claimed features: “the semiconductor device further comprises an inactive region surrounding each of the first and second active region of each group”.
Regarding claim 12, the cited prior art does not teach or fairly suggests, along with other
claimed features: “along the second direction, each of the plurality of first source connection line segments and each of the plurality of first gate connection line segments are located on a same side of one of the first active region or the second active region in a same active region group”.
Regarding claim 13, the cited prior art does not teach or fairly suggests, along with other
claimed features: “and along the second direction, each of the plurality of first drain connection line segments and each of the plurality of first gate connection line segments are located on a same side of one of the first active region or the second active region in a same active region group.”.
Regarding claim 14, the cited prior art does not teach or fairly suggests, along with other
claimed features: “and along the first direction, the second source connection line segment and the second gate connection line segment are located on a same side of the plurality of active region groups”.
Regarding claim 15, the cited prior art does not teach or fairly suggests, along with other
claimed features: “and along the first direction, the second drain connection line segment and the second gate connection line segment are located on a same side of the plurality of active region groups”.
Regarding claim 16, the cited prior art does not teach or fairly suggests, along with other
claimed features: “a vertical projections of the plurality of first gate connection segments partially overlaps with vertical projections of the plurality of first source connection segments”.
Regarding claim 17, the cited prior art does not teach or fairly suggests, along with other
claimed features: “a vertical projections of the plurality of first gate connection segments partially overlaps with vertical projections of the plurality of first drain connection segments”.
Response to Arguments
Applicant’s arguments filed on 08/19/2026 have been fully considered but they
are not persuasive.
Applicant’s arguments with respect to the reference of Mizan are moot since this reference is no longer used in the rejection of the claims as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the reference of Lin_843, the applicant states that Lin “shows in its figures and describes in its specification partial overlap between the source pad area (SPA) and the drain interconnect region (DA), as well as partial overlap between the drain pad area (DPA) and the source interconnect region (SA), such partial overlap, by itself, does not disclose or suggest that the bonding pad is disposed above the two-dimensional electron gas”. The office respectfully disagrees with this statement. In the rejection of claim 1, on page 7, paragraph 13, of this office action, the electrode bonding pad is formed by elements #280 and #290. As one can see in Fig.8, elements #280 and #290 extend beyond the overlap area between regions SPA and DA (see Fig 6, the area extends over the length L1 corresponding to the vertical width of element #242) and the overlap area between regions DPA and SA (see Fig 6, the area extends over the length L2 corresponding to the vertical width of element #252). In Fig.8, elements #280 and #290 extend beyond elements #242 and #252, and into the region DA, and therefore a part of each one of them is disposed above the two dimensional gas located in the active region. Even if elements #242 and #252 are mapped as the electrode bonding pad, one can see in Fig.7B and 7C, which show cross-sectional views in the overlap region, the presence of layers #112 and #114, where the electron gas is located at the interface between these two layers (column 7, rows 60-67, column 8, rows 1-2).
The applicant further states that “Lin expressly limit the foregoing overlap to no more than 40% of the area of the corresponding interconnect region, and preferably to 1%-20%”. The overlap area refers to elements #242 and #252 and not elements #280 and #290 which have a larger overlap with the interconnect region as shown in Fig.8. While Lin_843 does not disclose the size of the overlap area of elements #280 and #280 with the interconnect region, note that the current application does not disclose it either. In paragraph [0059], the current application states:” For example, in some embodiments of the present application, at least a part of the source bonding pad 1411 is located in the active region aa, and/or at least a part of the drain bonding pad 1412 is located in the active region aa. Specifically, it may be that all of the source bonding pad 1411 and all of the drain bonding pad 1412 are located in the active region aa, or it may be that the at least a part of the source bonding pad 1411 and the at least a part of the drain bonding pad 1412 are located in the active region aa, or it may be that only the at least a part or all of the source bonding pad 1411 is located in the active region aa, or it may be that only the at least a part or all of the drain bonding pad 1412 is located in the active region aa, which is not limited in the embodiments of the present application.” No parts of the specification appear to include any information regarding the minimum amount of overlap of the bonding pads with the active region, and therefore, the current application fails to show the criticality of this parameter.
Applicant also states that: “Lin teaches providing a relatively thick insulating layer having a thickness greater than 7 um between the bonding pad and the underlying structure, thereby physically separating the bonding pad from the underlying structure and reducing capacitive coupling”. No parts of the specification appear to include any information regarding the thickness of the dielectric layers and therefore the current application fails to show the criticality of this parameter.
Therefore, applicant arguments are not considered persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the maiLin_843g date of this action. In the event a first reply is filed within TWO MONTHS of the maiLin_843g date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the maiLin_843g date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the maiLin_843g date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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