Office Action Predictor
Last updated: April 16, 2026
Application No. 18/436,323

ELECTRONIC DEVICE INCLUDING A SENSOR AND A METHOD OF USING THE SAME

Final Rejection §102
Filed
Feb 08, 2024
Examiner
POTHEN, FEBA
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries, LLC
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
93%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
498 granted / 616 resolved
+12.8% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
45 currently pending
Career history
661
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 616 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 12/2/25 have been fully considered but they are not persuasive. Regarding claim 12, Applicant's arguments filed 12/02/25 have been fully considered but they are not persuasive. Applicant argues “Therefore, Kim does not disclose a wiring in the crack detection unit overlapping or underlapping a wiring within the scribe lane guard structure or the chip guard structure”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. overlapping or underlapping a wiring within the scribe line) are not recited in the rejected claim(s). The terms “a wiring within the scribe line” are not even recited in the claim language. The claim only recites that a portion of a sensor section overlaps/ underlaps a portion of a first interconnect. Lee teaches an edge guard 52 as well as a sensor part 64 which are in alignment with each other and can be considered to extend past the guard ring as the claims do not provide any directional limitations of the positions of the interconnect and the sensor. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 4. Claim(s) 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al., KR 20170042206 Regarding claim 12, Lee discloses an electronic device, comprising: an edge guard ring including a first interconnect (Fig. 1a-3b; guard ring structure 52); and a first sensor electrically insulated from the edge guard ring (Fig. 1a-3b; crack detecting portion 54 having wiring structure 64 and 68), wherein: the first sensor includes a first terminal tab, a second terminal tab, and a sensor section extending from the first terminal tab to the second terminal tab (Fig. 1a-3b; pattern 64b or 64d end portion to the circuit portion 72 having input and output), and at least a portion of the sensor section overlaps or underlaps a portion of the first interconnect (Fig. 1a-3b; guard structure 52 in multiple levels and around the die as is the wiring structure ). Regarding claim 13, Lee discloses wherein: the edge guard ring further includes a second interconnect, and the second interconnect and the sensor section lie at a same interconnect level (Fig 3b; wiring pattern 68 on a same level as 52e, wiring pattern 64 on a same level as 52c). Regarding claim 14, Lee discloses wherein: the sensor section has a sensor length, and along at least 80% of the sensor length, the at least a portion of the sensor section underlaps or overlaps the first interconnect (Fig. 1a-1b). Allowable Subject Matter Claims 1-11, 15-24 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, prior art does not disclose or suggest: “wherein: the first sensor and the second sensor are different sensors, and the first portion and the second portion are different portions of the peripheral edge of the die, and the electronic device is adapted such that: when the first sensor access transistor is on and all other sensor access transistors not coupled to the first sensor are off, current can flow through the first sensor and no current flows through any other sensor in the die, and when the second sensor access transistor is on and all other sensor access transistors not coupled to the second sensor are off, current can flow through the second sensor and no current flows through any other sensor in the die” in combination with all the limitations of claim 1. Regarding claim 15, prior art does not disclose or suggest: “the first sensor is adjacent to a first portion of a peripheral edge of the die, the first pair of sensor access transistors is electrically coupled to opposite ends of the first sensor, the second sensor is adjacent to a second portion of the peripheral edge of the die, the second pair of sensor access transistors is electrically coupled to opposite ends of the second sensor, and obtaining the first electrical parameter is performed while the first pair of sensor access transistors is on and all other sensor access transistors are off; and obtaining a second electrical parameter associated with the second sensor while the second pair of sensor access transistor is on and all other sensor access transistors are off and determining whether or not a first crack in the die is adjacent to or extends through the first sensor or whether or not a second crack in the die is adjacent to or extends though the second sensor” in combination with all the limitations of claim 15. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEBA POTHEN whose telephone number is (571)272-9219. The examiner can normally be reached 8:30-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEBA POTHEN/ Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Feb 08, 2024
Application Filed
Sep 06, 2025
Non-Final Rejection — §102
Dec 02, 2025
Response Filed
Mar 05, 2026
Final Rejection — §102
Apr 10, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601672
SENSITIVITY AMPLIFICATION TECHNIQUES FOR MAGNETOCHEMICAL SENSORS
2y 5m to grant Granted Apr 14, 2026
Patent 12596087
SYSTEM AND METHOD FOR MEASURING CONDENSATION AND/OR ADVANCE OF CORROSION
2y 5m to grant Granted Apr 07, 2026
Patent 12584900
METHOD, KIT, AND SENSOR FOR DETECTING ANTIBODY OF INTEREST IN WASTEWATER
2y 5m to grant Granted Mar 24, 2026
Patent 12571840
Array of Through-Silicon Via Contact Points on a Semiconductor Die
2y 5m to grant Granted Mar 10, 2026
Patent 12566221
Power Distribution Busway Testing
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
93%
With Interview (+11.9%)
2y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 616 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in for Full Analysis

Enter your email to receive a magic link. No password needed.

Free tier: 3 strategy analyses per month