DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on February 8, 2024 was considered by the examiner during the course of the prior office action. Secondary acknowledgement copy provided with this action to correct an error with the signature block.
Response to Amendment
The amendment filed February 2, 2026 has been entered. Claims 1-2, 6, 8-9, 13, 15-16, and 19 remain pending in this application. Claims 3-5, 7, 10-12, 14, 17-18, and 20 have been cancelled at applicant’s request. Claims 1, 6, 8, and 15 have been amended, adding no new matter. No claims have been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding original Claim 13: Claim 13 begins, “The apparatus of claim 10, further comprising…” Claim 10 has been cancelled at applicant’s request, leaving Claim 13 without valid dependency. In the interest of compact prosecution, Claim 13 will be interpreted as depending from Amended Claim 8, instead.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 6, 8-9, 13, 15-16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,917,554 B2 to Fumiaki Toyama, et al. (hereafter Toyama) in view of US 11,527,292 B2 to Ke Liang, et al. (hereafter Liang).
Regarding Amended Independent Claim 1, Toyama discloses a non-volatile storage system, comprising:
a substrate including a word line switch well region (A word line switch well region for a non-volatile storage device: Toyama, col.3:2-4);
a plurality of memory blocks (Disclosing multiple memory blocks: Toyama, col.3:2-4), said memory blocks including
non-volatile memory arrays (Disclosing a memory array: Toyama, Figure 4A) with a plurality of memory strings of non-volatile storage elements (Showing strings of non-volatile memory storage elements: Toyama, Figure 2)
arranged into rows and columns (Memory elements arranged in rows and columns: Toyama, Figure 2) over the word line switch well region (Showing the word line switch transistors 327, 347, and 367, below memory cells 322-326 and similar: Toyama, Figure 2) and including
a plurality of word lines, each word line being coupled to one or more rows of non-volatile storage elements (A plurality of Wordlines WL0-WL3: Toyama, Figure 2); and
control circuitry in communication with the non-volatile memory arrays (Control circuitry 220 connected to memory array 200: Toyama, Figure 4A),
the control circuitry configured to apply a negative voltage to the word line switch well region (Applying a negative voltage to the word line switch well region: Toyama, col.5:59-60).
Toyama does not disclose that during an erase operation on a selected block, a negative voltage is applied to the word lines of an unselected block. Liang, however, discloses a non-volatile storage system, including during an erase operation (Disclosing an erase operation comprising multiple steps, including pre-charging, erase, and erase verify steps: Liang, col.10:23-30) in a selected memory block of the plurality of memory blocks (The erase operation being of a selected block of memory: Liang, col.10:8-10) and to apply, during the erase operation, a negative voltage to the word lines of an unselected memory block of the plurality of memory blocks (Applying a negative Vdis to unselected word lines following the start of the erase phase: Liang, col.11:43-48).
Liang teaches applying a zero or negative discharge voltage to the word lines of an unselected block can help resolve leakage current issues and help reduce the size of the driving transistor (Liang, col. 11:7-8).
Therefore, it would have been obvious, before the effective filing date of this application, to combine the zero or negative discharge voltage technique of Liang with the negative word line switch well configuration of Toyama, with a reasonable expectation of success. Both inventions are well known in the field of controlled memory array erasure, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 9 and 16, Toyama discloses the non-volatile storage system of claim 1, wherein
the word line switch well region is a p-well region (The word line switch well region is a p-well region 492: Toyama, col.5:43 and Figure 3A).
Regarding Amended Claim 6 and the substantially similar limitations of Claims 13 and 19, Toyama discloses the non-volatile storage system of claim 1, further comprising:
a plurality of bit lines,
each bit line of the plurality bit lines is coupled to one or more columns of the non-volatile storage elements (Showing bit lines coupled to one or more columns of memory storage elements: Toyama, Figure 2); and
wherein the erase operation includes floating the plurality of bit lines (The erase operation including floating the bit lines: Toyama, col.18:35-39).
Regarding Amended Independent Claim 8, Toyama discloses an apparatus, comprising:
a substrate including a word line switch well region (A word line switch well region for a non-volatile storage device: Toyama, col.3:2-4);
a plurality of memory blocks (Disclosing multiple memory blocks: Toyama, col.3:2-4) including
non-volatile memory arrays (Disclosing a memory array: Toyama, Figure 4A) including a plurality of memory strings of non-volatile storage elements (Showing strings of non-volatile memory storage elements: Toyama, Figure 2)
(Memory elements arranged in rows and columns: Toyama, Figure 2) over the word line switch well region (Showing the word line switch transistors 327, 347, and 367, below memory cells 322-326 and similar: Toyama, Figure 2);
a plurality of word lines, each word line is coupled to one or more rows of non-volatile storage elements (A plurality of Wordlines WL0-WL3: Toyama, Figure 2); and
circuitry (Control circuitry 220 connected to memory array 200: Toyama, Figure 4A) configured to apply a negative voltage to the word line switch well region (Applying a negative voltage to the word line switch well region: Toyama, col.5:59-60).
Toyama does not disclose that during an erase operation on a selected block, a negative voltage is applied to the word lines of an unselected block. Liang, however, discloses a non-volatile storage system, including during an erase operation (Disclosing an erase operation comprising multiple steps, including pre-charging, erase, and erase verify steps: Liang, col.10:23-30) in a selected memory block of the plurality of memory blocks (The erase operation being of a selected block of memory: Liang, col.10:8-10) and to apply, during the erase operation, a negative voltage to the word lines of an unselected memory block of the plurality of memory blocks (Applying a negative Vdis to unselected word lines following the start of the erase phase: Liang, col.11:43-48).
Liang teaches applying a zero or negative discharge voltage to the word lines of an unselected block can help resolve leakage current issues and help reduce the size of the driving transistor (Liang, col. 11:7-8).
Therefore, it would have been obvious, before the effective filing date of this application, to combine the zero or negative discharge voltage technique of Liang with the negative word line switch well configuration of Toyama, with a reasonable expectation of success. Both inventions are well known in the field of controlled memory array erasure, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 15, Toyama discloses a method of operating a non-volatile semiconductor memory device, the method comprising:
applying a negative voltage to a word line switch well region of a substrate during an erase operation (Applying a negative voltage to the word line switch well during an erase operation: Toyama, col.3:26-28),
wherein a non-volatile memory array including a plurality of memory strings of non-volatile storage elements are arranged into rows and columns (Memory elements arranged in rows and columns: Toyama, Figure 2)
over the word line switch well region (Showing the word line switch transistors 327, 347, and 367, below memory cells 322-326 and similar: Toyama, Figure 2).
Toyama does not disclose applying a negative voltage to word lines of an unselected block of memory cells during an erase operation in a selected block of memory cells. Liang, however, discloses a non-volatile storage system, including applying a negative voltage (Applying a zero or negative discharge voltage to unselected wordlines: Liang, col.11:43-48) to word lines of an unselected block of memory cells (The negative discharge voltage applied to word lines of the unselected block: Liang, col.11:9-10).
Liang teaches applying a zero or negative discharge voltage to the word lines of an unselected block can help resolve leakage current issues and help reduce the size of the driving transistor (Liang, col. 11:7-8). Therefore, it would have been obvious, before the effective filing date of this application, to combine the zero or negative discharge voltage technique of Liang with the negative word line switch well configuration of Toyama, with a reasonable expectation of success. Both inventions are well known in the field of controlled memory array erasure, and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed February 2, 2026 have been fully considered but they are not persuasive.
Applicant makes two arguments, the first being prior art Toyama fails to disclose the application of a negative bias voltage to unselected word lines during an erase operation and, in fact, teaches away from such an operation (Applicant’s Argument, p.11 ¶2). This amounts to a piecemeal analysis of the prior art. It is acknowledged Toyama fails to teach the application of the negative bias voltage, which is why Liang is cited for this purpose. It is irrelevant that Toyama teaches away from this configuration as Liang provides the reason for combining the references. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s second argument is that Liang also fails disclose the application of a negative bias voltage to unselected word lines during an erase operation, instead only applying the negative bias during a pre-charging operation and then floating the unselected word lines during the erase operation (Applicant’s Argument, p.11 ¶2). Ultimately, this argument is unpersuasive, although there is evidence on both sides of the scale.
First, it may be argued the erase operation is a multi-step process, including at a minimum the erase stage and the erase verify stage (“[I]n both erase and erase verify stages of the erase operation”: Liang, col.10:16-17). Broadest reasonable interpretation would include the pre-charge stage in the overall erase operation. Liang itself makes this argument ambiguous, however, stating, “As shown in FIG. 7, an erase operation starts at time T1…” (Liang, col.10:37). Figure 7 does not clearly disclose time T1 as excluding the pre-charging stage, but the similar timepoint in FIG. 8 unambiguously excludes the pre-charge phase.
Secondly, as Applicant acknowledges, Liang states, “[I]n the second time period between time T1 and time T2 (e.g., corresponding to the erase stage and erase verify state of an erase operation), the voltage applied to unselected word line 318b is in a floating state, according to some implementations.” (Liang, col.12:11-15, typographical error in the original). This sentence is also ambiguous, at best. The key phrase being, “according to some implementations,” suggesting alternative implementations in which the unselected word lines are not left to float.
In contrast to the above, Liang is unambiguous in one section, found in column 11, lines 42-48.
In one example, the discharge voltage may be 0 V. In another example, the discharge voltage may be a negative bias voltage. Compared with the known approach, for example shown in FIG. 7, the voltage at time T1 (when the erase stage starts) can be reduced from the initial voltage (Vdd, shown in FIG. 7) to the discharge voltage (Vdis, shown in FIG. 8).
This clearly discloses the discharge voltage – expressly applied to unselected word lines (Liang, col.11:35-37) – being both negative and applied after time T1, during the erase stage. In light of this disclosure, applicant’s argument is found unpersuasive. Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,950,309 B2 to Shigekazu Yamada, et al.: Teaching applying a 0V signal to wordlines of unselected blocks during an erase operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/UYEN SMET/Primary Examiner, Art Unit 2824