DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 3-6, 9-12, and 14 are pending.
Claims 1, 3-6, and 10 are amended.
Claims 2, 7-8, and 13 are cancelled.
Claim Rejections - 35 USC § 112
Applicant’s amendment of claim 10 to change the term “implemented in” to “formed in” overcomes the rejection of 04/08/2026 under 35 U.S.C. 112b. The rejection of claims 10-12 under 35 U.S.C. 112(b) is withdrawn.
Response to Arguments/Amendments
Applicant’s arguments, see pages 4-6, filed 04/30/2026, with respect to the rejections of amended independent claim 1 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Specifically, the amendment of claim language to include “a p-type GaN material disposed over a front barrier layer and a gate electrode disposed over the p-type GaN material” overcomes the embodiment of the prior art rejection of record. Therefore, the rejection has been withdrawn. Accordingly, the rejections of dependent claims 3-6, 9-12, and 14 are withdrawn. However, upon further consideration, a new grounds of rejection is made in view of an alternative embodiment of Okamoto et al. (US PGPub 2010/0320505).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamoto et al. (US PGPub 2010/0320505; herein known as Okamoto).
Regarding claim 1, Okamoto teaches (Fig. 9B) an enhancement mode gallium nitride (GaN) transistor ([0116]), comprising: a source (5, [0124]), a gate ([0125]) and a drain (6, [0123]), wherein the gate comprises a p-type GaN material (25, [0116]) disposed over a front barrier layer (4, [0121]) and a gate electrode (7, [0125]) disposed over the p-type GaN material (25, [0122]), and a hole collector electrode (8, [0126]), wherein the gate electrode (7, [0125]) and the hole collector electrode (8, [0126]) contact the p-type GaN material (25, [0116]) of the gate (see Figure), and wherein, when a negative voltage is applied to the hole collector electrode, holes accumulating in the p-type GaN material of the gate are removed. Application of a negative voltage to the hole collector electrode of Okamoto would switch the transistor to its “on” state, during which time the hole collector electrode, in contact with the p-type GaN material, would necessarily conduct holes from the p-type GaN material-of the gate and remove them from the device.
Regarding claim 3, Okamoto teaches (annotated Fig. 9B below) the enhancement mode GaN transistor of claim 1, wherein the hole collector electrode (8, [0126]) is laterally spaced (L1) from the gate electrode (7, [0125]) on a top surface of the p-type GaN material of the gate.
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Regarding claim 4, Okamoto teaches (Fig. 9B) the enhancement mode GaN transistor of claim 3, wherein the hole collector electrode (8, [0126]) contacts the top surface of the p-type GaN material of the gate (4, [0122]). See Fig. 9B.
Regarding claim 5, Okamoto teaches (Fig. 9B) the enhancement mode GaN transistor of claim 3, wherein the hole collector electrode (8, [0121]) extends into a recess (28, [0121]) in the p-type GaN material (4, [0121]) of the gate ([0121]). See Fig. 9B.
Regarding claim 6, Okamoto teaches (Fig. 9B) the enhancement mode GaN transistor of claim 3, wherein the hole collector electrode (8, [0121]) extends completely through the GaN material (4, [0121]) of the gate. See Fig. 9B.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okamato as applied to claim 1 above, in view of Wu et al. (US PGPub 2014/0015066; known herein as Wu).
Regarding claim 9, Okamato teaches the enhancement mode GaN transistor of claim 1, and teaches wherein the hole collector electrode is electrically connected to a component providing a voltage ([0068]), and in order to function as a hole collector electrode as taught, the hole collector electrode of Okamato must inherently be electrically connected. Okamato does not explicitly teach a negative voltage generating circuit.
Wu teaches (Fig. 6) a negative voltage generating circuit ([0050]).
Because Okamato and Wu are directed toward enhancement mode GaN transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamato and Wu to include a negative voltage generating circuit in order to induce electron recombination (Wu, [0062]).
Regarding claim 10, Okamato in view of Wu teaches the enhancement mode GaN transistor of claim 9, wherein the negative voltage generating circuit is formed in GaN and is integrated with the transistor. Wu teaches wherein the circuit components are part of a HEMT device. ([0003]).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Okamato in view of Wu, as applied to claim 10 above, and further in view of Ming et al. (US PGPub 2020/0052687; herein known as Ming).
Regarding claim 11, Okamatu in view of Wu teaches the enhancement mode GaN transistor of claim 10, but does not explicitly teach wherein the negative voltage generating circuit comprises a charge pump to generate the negative voltage.
Okamatu in view of Wu teaches a circuit capable of providing negative voltage to a HEMT.
Ming teaches a charge pump ([0069]) which provides voltage to a HEMT when a certain threshold voltage is exceeded ([0069]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the voltage source of Okamatu in view of Wu with the charge pump of Ming, for the predictable result of providing voltage to the GaN transistor. See MPEP 2143.I.B.
Regarding claim 12, Okamatu in view of Wu and Ming teaches wherein the negative voltage generating circuit comprises circuitry for sensing the negative voltage and activating the charge pump when needed (Ming, [0069)]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Okamato as applied to claim 1 above, in view of Mandelli et al. (US PGPub 2019/0246051; herein known as Mandelli).
Regarding claim 14, Okamato teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the negative voltage is provided externally through an I/O terminal.
Mandelli teaches wherein the negative voltage ([0030]) is provided externally through an I/O terminal ([0027]; Pixel 300 is compatible with the image sensor 200, which contains I/O circuitry).
Because Okamato and Mandelli are both directed toward enhancement mode GaN transistors for hole collection, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamato and Mandelli to include wherein the negative voltage is provided externally through an I/O terminal in order to convey pixel signals to other circuitry for processing (Mandelli, [0027]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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