Prosecution Insights
Last updated: October 25, 2026
Application No. 18/436,507

DESIGN METHOD AND DESIGN SYSTEM FOR PLACING AND ROUTING SEMICONDUCTOR DEVICES

Non-Final OA §102
Filed
Feb 08, 2024
Priority
Dec 12, 2023 — RE 10-2023-0179665
Examiner
ALAM, MOHAMMED
Art Unit
Tech Center
Assignee
Yu Mi Lee
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
789 granted / 856 resolved
+32.2% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
10 currently pending
Career history
865
Total Applications
across all art units

Statute-Specific Performance

§101
22.6%
-17.4% vs TC avg
§103
12.5%
-27.5% vs TC avg
§102
57.9%
+17.9% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 856 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Non-Final Office Action DETAILED ACTION Examiner’s Notes (a) Claim date: 02/08/2024. (b) Priority date: 12/12/2023. Claim Rejections - 35 USC 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1, 12, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Stevens” <US 20050148243 A1>.(As to claim 1, Stevens discloses):1. A design method for placing and routing a semiconductor device in a computer system, the design method comprising [0081: “the above described embodiments of the invention and variations of the such embodiments may be implemented in software operating on a general or special purpose computer.”]: placing, by the computer system, a plurality of semiconductor devices in a design region [0002: “A typical electronics apparatus or system includes a plurality of components and electrical traces interconnecting the components.” Describing placing electronic components.]; PNG media_image1.png 472 430 media_image1.png Greyscale calculating and evaluating, by the computer system, a routing path between the plurality of semiconductor devices, based on a first algorithm; calculating, by the computer system, the routing path between the plurality of semiconductor devices based on a result calculated through the first algorithm and a second algorithm, based on an evaluation result, and [0025: “The process illustrated in FIG. 2 optimizes the traces by assigning forces to nodes that compose the traces and then moving the nodes in accordance with the forces”] [0036: obstacle 440 has “a first zone 442 and a second Zone 444…a force is assigned to each Zone.” The force-based node movement (second algorithm) operates on the graph-generated traces (first algorithm) and repeats based on the design rule check (evaluation result)] comparing the result calculated through the first algorithm with a result calculated through the second algorithm [0049: “length of a shortest or approximately shortest line segment between the two obstacles is determined, and then, using the minimum trace-to-obstacle clearance, minimum trace-to-trace clearance, and maximum trace width clearance received at step 202 of FIG. 2, the number of traces that may pass between the obstacles is determined. If the number of traces that have been routed between the obstacles exceeds the number of trace”]; and PNG media_image2.png 534 378 media_image2.png Greyscale verifying the result calculated through the first algorithm, based on a comparison result [Fig. 7, 708]. (As to claim 12, Stevens discloses):12. A computer-readable recording medium having program to execute design method of claim 1, in link to a computer implemented in hardware [0081: “implemented in specially designed hardware or a combination of software and special purpose hardware.”]. Allowable Subject Matter The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 2-11. Conclusion The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Feb 08, 2024
Application Filed
Oct 09, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.2%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 856 resolved cases by this examiner. Grant probability derived from career allowance rate.

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