DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to Application 18/436,602 filed on 02/08/2024. Claims 1-20 are pending in the office action.
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because the drawings submitted on 06/21/2024, the details (letter/characters) are blurred (see fig. 1 and fig. 4-9B for example). Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1: recited “a die-to-die interconnect” and “a first module” and “second module” which are unclear the relationship between “a first module” and “second module” to die-to-die interconnection and also unclear how “a first module” and “second module” structure relationship such that the first module and the second module are located on the same die or different die. Application’s fig. 1 and paragraph [0029], described three main blocks 110, 140, and WCHB pipeline (including set of WCHB 120 and 130), but doubt the relationship of these blocks.
Claims 1, 11, and 20: recited “a first synchronous domain”, “a second synchronous domain”, and “a dual-rail quasi-delay-insensitive format” are not defined in the claims, the Application specification does not provide standard for ascertain the requisite degree of “synchronous” and “quasi-delay-insensitive”, and one of ordinary skill in the art would not be reasonably appraised of the scope of claimed invention. Therefore, the phrase “a first synchronous domain”, “a second synchronous domain”, and “a dual-rail quasi-delay-insensitive format” are indefinite. In the other words, Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “synchronous domain” in claims 1, 11, and 20 are used by the claim to mean “clock signal,” while the accepted meaning is “clock signal.” The term is indefinite because the specification does not clearly redefine the term.
For the broadest interpreted based on specification, there are number of blocks (at least 2 blocks) as delay/buffer/clock blocks may be located on a same die or on different die and are connected to each other to produce a difference clock signal.
Claims 2-10 and 12-19 are also rejected because are depended directly or indirectly from claim 1 and 11, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 10-12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giaconi et al., (U.S. Pub. 2017/0126425) in view of Vivet et al., (A 4x4x2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links, IEEE, January 2017, Vol., 52, pages 33-49).
As per claims 1 and 11: Giaconi teaches a device (‘425, fig. 1, 100) having Chronos Channel Interconnects to transmit data using delay insensitive (DI) and quasi-delay-insensitive (QDI) logic (‘425, the abstract) comprising:
a first module configured to convert data from a first synchronous domain (i.e., clock domain) to a dual-rail quasi-delay-insensitive (QDI) format (‘425, fig. 1, 110, par. [0040] – [0046], “clock domain A” and “synchronous data input” (par. [041]), the abstract and par. [0067], “a dual-rail QDI”); and
a second module configured to convert the data from the dual-rail quasi-delay-insensitive format to a second synchronous domain (‘425, fig. 1, 120, par. [0040] – [0046], “clock domain B” and “synchronous data output” (par. [0045]), the abstract and par. [0067], “a dual-rail QDI”).
Gaiconi does not teach a first die stacked with a second die; and a die-to-die interconnect connecting the first die and the second die.
Vevit teaches a 3D modular and scalable network-on-chip (NoC) architecture implemented (Vevit, page 33, the abstract and I. Introduction and State of the Art, col. 1, the 3D technology present a wide scope and defines a full set of different technology elements, such as Die-to-Die (D2D) assembly).
Vevit also teaches the NoC implemented using quasi-delay insentive (QDI) asynchronous logic (Vevit, page 35, col. 2) and the asynchronous pipeline stage (fig. 8) decouples the timing between the two circuit layers: from the bottom die router up to the top die router through the DFT stage and logical/physical interfaces (Vevit, page 38, col. 1, D. Asynchronous Pipe Parallel and fig. 8).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Vevit and Gaiconi to modify Gaiconi’s asynchronous communication between TX and RX blocks using Vevit’s 3D asynchronous links to connect the bottom die and the top die in 3D NoC (i.e., homogeneous stacking) to increase capacity as the same footprint and high-performance computing (Vevit, page 35, col. 1).
As per claims 2, 12, 20: Giaconi teaches a method for providing Chronos Channel Interconnects to transmit data using delay insensitive (DI) and quasi-delay-insensitive (QDI) logic (‘425, the abstract) comprising:
a first module configured to convert data from a first synchronous domain (i.e., clock domain) to a dual-rail quasi-delay-insensitive (QDI) format (‘425, fig. 1, 110, par. [0040] – [0046], “clock domain A” and “synchronous data input” (par. [041]), the abstract and par. [0067], “a dual-rail QDI”); and
a second module configured to convert the data from the dual-rail quasi-delay-insensitive format to a second synchronous domain (‘425, fig. 1, 120, par. [0040] – [0046], “clock domain B” and “synchronous data output” (par. [0045]), the abstract and par. [0067], “a dual-rail QDI”).
Gaiconi does not teach a first die stacked with a second die; and a die-to-die interconnect connecting the first die and the second die, and a hybrid bonding for coupling between the first module of the first die and the second module of the second die.
Vevit teaches a 3D modular and scalable network-on-chip (NoC) architecture implemented (Vevit, page 33, the abstract and I. Introduction and State of the Art, col. 1, the 3D technology present a wide scope and defines a full set of different technology elements, such as Die-to-Die (D2D) assembly, wafer bonding (i.e., hybrid bonding), as well as Face-to-Face (F2F)).
Vevit also teaches the NoC implemented using quasi-delay insentive (QDI) asynchronous logic (Vevit, page 35, col. 2) and the asynchronous pipeline stage (fig. 8) decouples the timing between the two circuit layers: from the bottom die router up to the top die router through the DFT stage and logical/physical interfaces (Vevit, page 38, col. 1, D. Asynchronous Pipe Parallel and fig. 8), using different 3D technology a hybrid bond for coupling between the first module of the first die and the second module of the second die (Vevit, page 33, I. Introduction and State of the Art, col. 1, the 3D technology present a wide scope and defines a full set of different technology elements, such as Die-to-Die (D2D) assembly, wafer bonding (i.e., hybrid bonding), as well as Face-to-Face (F2F))
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Vevit and Gaiconi to modify Gaiconi’s asynchronous communication between TX and RX blocks using Vevit’s 3D asynchronous links to connect the bottom die and the top die in 3D NoC (i.e., homogeneous stacking) to increase capacity as the same footprint and high-performance computing (Vevit, page 35, col. 1).
As per claim 10: Gaiconi and Vevit teach wherein the first synchronous domain and the second synchronous domain are a same domain (‘425, fig. 2D, clockA (100MHz) and clockB (100MHz)).
Allowable Subject Matter
Claims 3-9 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if claims 3/13 and/or 7/17 is/are rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art record does not teach the following limitations:
As per claims 3 and 13: wherein the first module comprises: a first bisynchronous First-In First-Out (FIFO) buffer; a first weak-conditioned half-buffer (WCHB) layer; and a first converter configured to read from the first bisynchronous FIFO buffer and write to the first WCHB layer.
As per claims 7 and 17: wherein the second module comprises: a second WCHB layer; a second bisynchronous FIFO buffer; and a second converter configured to read from the second WCHB layer and write to the second FIFO buffer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/ Primary Examiner, Art Unit 2851
Prosecution Insights