CTNF 18/436,982 CTNF 79650 DETAILED ACTION Claims 1-31 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Applicant’s claim for the benefit of a prior-filed application (17/463,410) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Information Disclosure Statement Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/463,410 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application. In the IDS submitted on February 12, 2024, the examiner notes 1011-page and 1178-page NPL references, and a 146-page foreign patent document. In the IDS submitted on May 1, 2024, the examiner notes a 137-page NPL reference. In the IDS submitted on January 27, 2025, the examiner notes a 1513-page NPL reference. The examiner notes that 37 CFR 1.98(b)(5) requires citation of relevant pages. Relevant pages are those that are relevant/material to patentability of the claims. See 37 CFR 1.56(b) and MPEP 609.04(a) (“ Concise explanations (especially those which point out the relevant pages and lines) are helpful to the Office, particularly where documents are lengthy and complex and applicant is aware of a section that is highly relevant to patentability... ”). From MPEP 2004, item 5, “ [i]t is desirable to pick out the broadest claim or claims and measure the materiality of prior art against a reasonably broad interpretation of these claims. ” The examiner notes a number of pages in the aforementioned documents that appear to be irrelevant/immaterial to patentability of the claims (e.g., various instructions that do not appear to be of concern to applicant’s claimed invention). It is unrealistic to consider the examiner “fully informed” based on the presentation to him of “a mountain of largely irrelevant data from which he is presumed to have been able, with his expertise and with adequate time, to have found the critical data. It ignores the real world conditions under which examiners work.” (see Rohm & Haas Co. v. Crystal Chemical Co., 722 F.2d 1556 (Fed. Cir. 1983)). Applicant has a duty not just to disclose pertinent prior art references but to make a disclosure in such way as not to “bury” it within other disclosures of less relevant prior art (see Golden Valley Microwave Foods Inc. v. Weaver Popcorn Co. Inc., 24 USPQ2d 1801 (N.D. Ind. 1992); Molins PLC v. Textron Inc., 26 USPQ2d 1889, at 1899 (D.Del 1992); and Penn Yan Boats, Inc. v. Sea Lark Boats, Inc. et al., 175 USPQ 260, at 272 (S.D. Fl. 1972)). From MPEP 2004, item 13, “I[i]t is desirable to avoid the submission of long lists of documents if it can be avoided. Eliminate clearly irrelevant and marginally pertinent cumulative information. If a long list is submitted, highlight those documents which have been specifically brought to applicant' s attention and/or are known to be of most significance.” The examiner has considered the entirety of the first two documents listed above by considering the pages cited by the related cited foreign search reports and the pages related to compare instructions. The examiner has considered the entirety of the next two documents listed above by finding instances of “compare” (and variations thereof, e.g. comparison, cmp, etc.) and considering the context in which these instances appeared. In the last document listed above, the examiner considered the CMPPD, CMPPS, MAXPS, and MINPS instructions. If applicant is aware of other portions of these documents that are material to patentability, then applicant is respectfully requested to cite and direct the examiner to the pages that are most relevant (material to patentability) to the claimed invention. Until such time, the reference has been considered only as set forth above, which is consistent with MPEP 609.05(b) (“ Consideration by the examiner of the information submitted in an IDS means that the examiner will consider the documents in the same manner as other documents in Office search files are considered by the examiner while conducting a search of the prior art in a proper field of search. The initials of the examiner placed adjacent to the citations on the PTO/SB/08A and 08B or its equivalent mean that the information has been considered by the examiner to the extent noted above. ”). Specification The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends inserting --PACKED-- at the beginning and --TO STORE MAXIMUM OR MINIMUM DATA ELEMENTS-- at the end. 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. 07-29 AIA The disclosure is objected to because of the following informalities: In paragraph 49, line 1, it appears that “operand” should be replaced with --operands-- since there are multiple operands in step 301. In paragraph 54, it appears applicant instead meant --When the data element of a source is not-a-number, store the data element of the other source at 403.--. Sources aren’t not-a-number; data elements within sources could be not-a-number. In paragraph 68, line 1, it appears that “operand” should be replaced with --operands-- since there are multiple operands in step 701. In paragraph 73, it appears applicant instead meant --When the data element of a source is not-a-number, store the data element of the other source at 903.--. Sources aren’t not-a-number; data elements within sources could be not-a-number. In paragraph 88, line 1, it appears that “operand” should be replaced with --operands-- since there are multiple operands in step 1201. In paragraph 96, line 2, replace “compare” with --compares--. In paragraph 102, line 1, it appears that “operand” should be replaced with --operands-- since there are multiple operands in step 1501. In paragraph 120, line 4, remove the apostrophe from “GPGPU’s”. In paragraph 121, line 9, insert --computing-- after “(throughput)”. In paragraph 123, line 6, insert --computing-- after “(throughput)”. In paragraph 132, “a register maps” is grammatically incorrect . Appropriate correction is required. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: In FIG.2, 223; In FIG.6, 623; In FIG.10, 1023; and In FIG.14, 1433. FIGs.5, 9, 13, and 16 are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner recommends improving the quality of FIG.11. The drawings are objected to because of the following minor informalities: In FIG.2, destination 231 shows NaN stored twice. However, this conflicts with FIG.4, step 403, and FIG.5, which explains that NaN is never stored when the other corresponding element is not NaN. It appears that NaN would only be stored when both corresponding elements in both sources are NaN, and such is not the case in FIG.2. Either the specification or the drawing is incorrect. Please make them consistent. In FIG.3, step 307, it appears that “OPERAND(S)” should be replaced with --OPERANDS-- since step 301 sets forth multiple operands. How could the operation of FIG.2 be performed if both source operands are not retrieved? In FIG.4, step 403 should be reworded as proposed above for paragraph 54. In FIG.6, destination 631 shows NaN stored twice. However, this conflicts with FIG.8, step 803, and FIG.9, which explains that NaN is never stored when the other corresponding element is not NaN. It appears that NaN would only be stored when both corresponding elements in both sources are NaN, and such is not the case in FIG.6. Either the specification or the drawing is incorrect. Please make them consistent. In FIG.7, step 707, it appears that “OPERAND(S)” should be replaced with --OPERANDS-- since step 701 sets forth multiple operands. How could the operation of FIG.6 be performed if both source operands are not retrieved? In FIG.8, step 803 should be reworded as proposed above for paragraph 73. In FIG.10, please shift the text “PACKED DATA SOURCE 1 (SRC1) 1001” to the right to be closer to its lead line. In FIG.12, step 1207, it appears that “OPERAND(S)” should be replaced with --OPERANDS-- since step 1201 sets forth multiple operands. How could the operation of FIG.10 be performed if both source operands are not retrieved? In FIG.15, step 1507, it appears that “OPERAND(S)” should be replaced with --OPERANDS-- since step 1501 sets forth multiple operands. How could the operation of FIG.14 be performed if both source operands are not retrieved? In FIG.16, there are two instances of “ELIF”. Does applicant mean “ELSE IF” as used in FIGs.5 and 9? ELIF is not incorrect but the examiner wanted to point this out if applicant meant to be consistent. Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or amendment to the specification to add missing reference characters in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections/Recommendations Claim 1 (and similarly each of claims 9 and 16) is objected to because of the following informalities: The phrase “…elements are both zero, of either sign, the…” is grammatically incorrect. The examiner recommends rewording to --when each of the BF16 elements of the pair of corresponding BF16 data elements is one of positive zero or negative zero, the…--. Claim 4 (and similarly each of claims 5, 7-8, 12-13, 15, and 19-21) is objected to because of the following informalities: Replace “a NaN” with --not-a-number (NaN)--. The abbreviation should be spelled out before it is used the first time. 07-29-01 AIA Claim 17 (and similarly claim 20) is objected to because of the following informalities: Taking claim 17 as exemplary, in lines 1-2, applicant claims the medium comprises further instructions that perform the maximum comparison, which is performed by the decoded instruction in claim 16. Thus, it is not further instructions that cause the comparison. The examiner recommends rewording to --wherein the decoded instruction, when executed, is to cause the machine to perform the maximum comparison…--. In claims 24 and 29, the examiner recommends removing “packed” from the last line for consistency with claims 23, 25-26, 28, and 30-31 . Appropriate correction is required. 07-30-03-h AIA Claim Interpretation At least one claim is identified as including non-limiting contingent limitations. “ The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. ” “ The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. ” See MPEP 2111.04(II). Regarding claim 9, if all predicate values are the first value, then the last paragraph on page 3 is not part of the claimed method. If all predicate values are the second value, the 2 nd to last paragraph on page 3 is not part of the claimed method. In other words, the broadest reasonable interpretation (BRI) of claim 9 includes a method that does not include one of the last two paragraphs on page 3. If applicant wants all limitations to be required, the examiner recommends, for instance, inserting --determining that at least one of the predicate values is a first value;-- prior to the 2 nd to last paragraph on page, and then starting the next paragraph with --in response to determining that the at least one of the predicate values is the first value, the destination packed data operand includes…--. Then, prior to the last paragraph on page 3, applicant could insert --determining that at least a second one of the predicate values is a second value;-- followed by --in response to determining that the at least the second one of the predicate values is the second value, the destination packed operand includes…--. Regarding claim 10, when there are no predicate values of the first value, the BRI of the claim encompasses only the method of claim 9 (sans the 2 nd to last paragraph on page 3) and the maximum comparison. Regarding claim 11, when there are no predicate values of the first value, the BRI of the claim encompasses only the method of claim 9 (sans the 2 nd to last paragraph on page 3) and the minimum comparison. Regarding claim 12, when there are no predicate values of the first value, the BRI of the claim encompasses nothing more than the method of claim 9 (sans the 2 nd to last paragraph on page 3). Regarding claim 13, when there are no predicate values of the first value, the BRI of the claim encompasses nothing more than the method of claim 9 (sans the 2 nd to last paragraph on page 3). Regarding claim 14, when there are no predicate values of the second value, the BRI of the claim encompasses nothing more than the method of claim 9 (sans the last paragraph on page 3). Regarding claim 15, when there are no predicate values of the first value, the BRI of the claim encompasses only the method of claim 9 (sans the 2 nd to last paragraph on page 3), the maximum comparison, and the “unchanged” limitation at the end of claim 15. When, however, there are no predicate values of the second value, the BRI of the claim encompasses only the method of claim 9 (sans the last paragraph on page 3), the maximum comparison, and all other limitations in claim 15 except for the “unchanged” limitation at the end of claim 15. 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Such claim limitations are: In claim 16, line 2, “machine to perform operations”. These broad operations may include coextensive operations such as receiving data, storing data, and processing data, and, thus, the machine may include a processor (generally represented by FIGs.17-20(B)). In claim 16, lines 2-3, “machine to perform operations, including to…decode an instruction”. From FIG.20(A), this is interpreted to encompass a decode stage 2006 of a processor pipeline. In claim 16, lines 2 and 13, “machine to perform operations, including to…perform operations corresponding to the instruction”. These broad operations may include coextensive operations such as receiving data, storing data, and processing data, all of which are performed for the claimed instruction, and, thus, the machine may include a processor (generally represented by FIGs.17-20(B)). In claim 16, lines 2 and 14, “machine to perform operations, including to…generate a destination packed data operand”. Generic circuitry 211 and 611 are not structurally-described. Thus, from FIG.20(A), the machine to perform the generation is interpreted to encompass an execute stage 2016 of a pipeline. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The examiner notes that, in claim 16, line 2 and last line, “machine to perform operations, including to…store the destination packed data operand in a destination register” does not invoke 112(f) because the limitation recites structure (register) to perform the function. Thus, prong (C) of the 3-prong test above is not satisfied. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-21, 24-26, and 29-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims recite the following limitations for which there is a lack of antecedent basis: In claim 1, 6 th -7 th to last line, “the corresponding data element” because there are corresponding data elements of the destination operand and source operands. In claims 2-21, 24-26, and 29-31 each instance of “the corresponding data element” for similar reasoning. In claim 16, each instance of “the instruction” because there are instructions in lines 1 and 3. It is recommended that applicant claim “decoding a first instruction” and then use “the first instruction” for subsequent references to the same instruction. Claims 2-8, 10-15, and 17-21 are rejected due to their dependence on an indefinite claim. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-31 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Referring to step 1 of the Subject Matter Eligibility Test (hereafter “the test”), claims 1-15 and 22-31 are directed to a statutory category of invention. Claims 16-21 are directed to transitory embodiments (e.g. signals per se) and, thus, are not directed to a statutory category of invention. Referring to step 2A (prong 1) of the test, claim 1 recites to include in a destination packed data operand, for each of eight predicate values that is a first value, a corresponding data element that is a result of either a maximum comparison or a minimum comparison of the pair of corresponding BF16 data elements, wherein, when the BF16 data elements of the pair of corresponding BF16 data elements are both zero, of either sign, the corresponding data element is to include the BF16 data element from the second packed data operand; and to include in the destination operand, for each of eight predicate values that is a second value, a corresponding data element that is either zero or remains unchanged, wherein a BF16 data element of the first packed data operand has a sign bit, an 8-bit exponent, and a 7-bit fraction; wherein each input has eight BF16 data elements, each of the at least eight BF16 data elements of the first packed data operand corresponding to a different one of the at least eight BF16 data elements of the second packed data operand in a same data element position, and each of the predicate values corresponding to a different pair of corresponding BF16 data elements . This activity is an abstract idea in the grouping of mental processes, in which a human can receive input vectors, compare corresponding elements, and construct an output vector with max or min values. A human can selectively do this for only some of the elements based on predicate data. For instance, see FIG.2. A human can trivially find the maximum amongst each corresponding pair of elements in inputs 201 and 203 and include that maximum in an output 231. Where there are zeros as claimed, or where predicates indicate unchanged data, a human can also appropriately set an output value in 231 as claimed. Referring to step 2A (prong 2) of the test, claim 1 recites the following additional elements: (1) A processor comprising: (1a) decode circuitry to decode an instruction, the instruction having a first field to identify a first packed data register, a second field to identify a second packed data register, and a third field to identify a predicate register, the first packed data register to store the first packed data operand, the second packed data register to store the second packed data operand, the predicate register to store the at least eight predicate values; and (1b) circuitry coupled to the decode circuitry to perform operations corresponding to the instruction, including to: (1b1) store the destination packed data operand in a destination register. The processor, decode circuity, circuitry coupled thereto, and packed registers are generic computing components used to perform the abstract idea. Furthermore, the instruction with fields to identify inputs of the operation amounts to a mere instruction to implement the abstract idea on a generic computer. The courts have deemed both of these types of elements as ones that do not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 6 th bullet). The examiner also notes that while packed registers are deemed generic, they are also deemed to constitute a link to a parallel/vector/SIMD environment (for performing multiple of the operations at the same time). Such has also been deemed by the courts as not integrating the abstract idea into a practical application (MPEP 2106.04(d)(I), last bullet). Finally, decoding an instruction and storing input and output data into packed registers is insignificant extra-solution activity that, per the courts, does not integrate the abstract idea into a practical application (MPEP 2106.04(d)(I), 7 th bullet). Regarding step 2B of the test, the courts have also determined that the generic computer components do not amount to significantly more (MPEP 2106.05(I)(A), 2 nd enumerated list, elements (i) and (iv)). Additionally, the retrieving and storing of data in registers does not amount to significantly more because the courts have recognized storing/retrieving information to/from memory (registers) as a well-known, routine, and conventional function (see MPEP 2106.05(d)(II), 1 st enumerated list, element (iv)). Finally, Official Notice is taken that decoding an instruction to ultimately perform its indicated operation was well understood, routine, and conventional before applicant’s invention. Thus, the decoding also does not amount to significantly more, per the courts. Overall, when the additional elements are considered individually or in combination, they do not amount to significantly more than the abstract idea and claim 1 is not patent eligible according to the test. Claims 2-8 merely set forth further aspects of the abstract idea, where the human is to perform maximum (claim 2) or minimum (claim 3), detect NaN values (which comprise a particular bit sequence) (claims 4-5), leave an element unchanged (claim 6), and perform a combination of these (claims 7-8), and create the output operand appropriately. Since there are no additional elements introduced by the claims, they are not patent-eligible for similar reasoning as claim 1. Claim 9 is rejected for similar reasoning as claim 1. Note also, that not all limitations are required by claim 9 due to contingent limitations so the reasoning related to the contingent limitations in the claim 1 rejection may be omitted for the purpose of rejecting claim 9. Claims 10-15 are rejected for similar reasoning as claims 2-7, respectively, when all limitations are considered. Alternatively, due to contingent limitations, some of the limitations of these claims are not required (see “Claim Interpretation” section above). As such, claims 10-11 only further set forth the abstract ideas of performing max/min (which are part of the abstract idea) and are secondly rejected for similar reasoning as claim 9 since the set forth no additional elements. Claims 12-14 set forth nothing beyond that in claim 9 and, thus, are secondly rejected for similar reasoning as claim 9. And, claim 15 sets forth performing max and the limitations related to one of those related to the predicate being the first value and those related to the predicate being the second value. Thus, claim 15 is secondly rejected for a subset of reasoning given for claims 7-8. Claim 16, despite not passing step 1 of the test, is anticipated to be not patent-eligible once applicant limits it to non-transitory embodiments and is, thus, mostly rejected for similar reasoning as claim 1. Further, a machine readable-medium to store instructions that when executed is to cause a machine to perform the claimed operations is a generic computer component (RAM, memory, cache, etc.), which does not integrate the abstract idea into a practical application, nor does it amount to significantly more, per the courts. Claims 17-21 are rejected for similar reasoning as claims 2, 6, 4, 3, and 4, respectively. Claim 22 includes a subset of limitations set forth in claim 1 and is, thus, rejected for a subset of reasoning set forth in the rejection of claim 1. Further, note that the opcode of the instruction is also part of a mere instruction to implement the abstract idea and, thus, it does not integrate into a practical application or amount to significantly more. Also, as described above, the storing is insignificant extra solution activity that does not integrate into a practical application or amount to significantly more. Claims 23-26 set forth selecting an element from an operand based on at least one detected condition, which is part of an abstract idea. The storing of the selected element, as described above, is insignificant extra solution activity that does not integrate into a practical application or amount to significantly more. Claim 27 includes a subset of limitations set forth in claim 1 and is, thus, rejected for a subset of reasoning set forth in the rejection of claim 1. Further, note that the opcode of the instruction is also part of a mere instruction to implement the abstract idea and, thus, it does not integrate into a practical application or amount to significantly more. Also, as described above, the storing is insignificant extra solution activity that does not integrate into a practical application or amount to significantly more. Claims 28-31 set forth selecting an element from an operand based on at least one detected condition, which is part of an abstract idea. The storing of the selected element, as described above, is insignificant extra solution activity that does not integrate into a practical application or amount to significantly more. Claims 16-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claims 16-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the BRI of “machine-readable storage medium” covers transitory propagating signals, which are non-statutory. For instance, paragraphs 190-192 of the specification do not limit the medium to non-transitory embodiments. To overcome this rejection, applicant should insert --non-transitory-- before “machine-readable”. Such an amendment is not considered new matter. See the "Subject Matter Eligibility of Computer Readable Media" memo dated January 26, 2010 (OG Cite: 1351 OG 212; OG Date: 23 Feb 2010). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-31 are rejected under 35 U.S.C. 103 as being unpatentable over Bradbury et al. (US 9,785,435) (as cited by applicant), in view of Wikipedia (“bfloat16 floating-point format”) (as cited by applicant) . Referring to claim 1, Bradbury has taught a processor comprising: decode circuitry (FIG.1B, 122) to decode an instruction (FIG.3A) , the instruction having a first field to identify a first packed data register (FIG.3A, field 308 identifies packed register V3, which may store multiple elements (column 10, lines 28-32)) , a second field to identify a second packed data register (FIG.3A, field 306 identifies packed register V2, which may store multiple elements (column 10, lines 28-32)) , the first packed data register to store a first packed data operand having multiple floating-point data elements, the second packed data register to store a second packed data operand having multiple floating-point data elements, each of the multiple data elements of the first packed data operand corresponding to a different one of the multiple data elements of the second packed data operand in a same data element position (again, see column 10, lines 28-32. A vector maximum instruction would compare corresponding floating-point elements in the same position in the two source registers) ; and circuitry (FIG.1B, execution circuitry 124) coupled with the decode circuitry to perform operations corresponding to the instruction, including to: generate a destination packed data operand, wherein: the destination packed data operand is to include a corresponding data element that is a result of either a maximum comparison or a minimum comparison of the pair of corresponding floating-point data elements (from FIG.4A and column 10, lines 28-35, note the results when the operands include +Fn and/or -Fn values. The result is the larger of the two) , wherein, when the floating-point data elements of the pair of corresponding floating-point data elements are both zero, of either sign, the corresponding data element is to include the floating-point data element from the second packed data operand (from FIG.4A, the second operand corresponds to (a). When (a) is +0 or -0, and first operand (b) matches (a), the result is T(a), which is the value from operand (a)) ; and store the destination packed data operand in a destination register (in FIG.3A, the instruction identifies destination register V1 in field 304, which stores the resulting packed operand (column 8, lines 56-60)) . Bradbury has not taught the instruction having a third field to identify a predicate register . However, Official Notice is taken that a predicate register having as many elements as other source operands was well known in the art before applicant’s invention. Such a register is useful to realize additional flexibility in processing by individually enabling or disabling vector operations of different lanes. For instance, if there are eight maximum operations to be performed on eight pairs of floating-point values, the predicate register would be known to have eight elements, each being set to 0 to disable a corresponding maximum operation on a respective pair, or set to 1 to enable a corresponding maximum operation on a respective pair. These predicate registers (also known as mask registers) are widely used in the field of SIMD/packed/vector processing, particularly to implement conditional branching where only some lanes would be required to perform an operation based on some condition. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury’s instruction to have a third field to identify a predicate register . Bradbury has also not taught the first packed data register to store a first packed data operand having at least eight BF16 data elements, and the second packed data register to store a second packed data operand having at least eight BF16 data elements . However, Bradbury has taught that the instruction includes a field (M4) to configurably specify one of multiple different floating-point formats on which the maximum operation is to be performed (column 9, line 64, to column 10, line 7). While BF16 is not disclosed by Bradbury, Wikipedia has taught the BF16 format as one that specifically reduces storage requirements while preserving the dynamic range of FP32 (see the first paragraph). One of ordinary skill in the art would have recognized that all formats ultimately represent sequences of binary data, which may be compared the same way. As a result, in order to store less data to represent floating-point values, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury such that one of the selectable formats on which to perform a maximum operation includes BF16, such that each packed data operand includes multiple BF16 data elements. Additionally, Official Notice is taken that packing eight elements into a register (including packing eight 16-bit elements into a 128-bit packed register) was well known in the art before applicant’s invention. The amount of elements packed is partly based on register size, and changing the register size is deemed a routine expedient, not a patentable distinction, particularly absent a demonstration of criticality of applicant’s register size and degree of packing (see MPEP 2144.04, including section (IV)(A)). One of ordinary skill in the art understands that, regardless of register size and element size (which indicates how many elements would be packed into a register), the maximum operation itself is not affected, as the number of parallel max operations to be performed may simply be scaled to match the number of pairs of elements to be compared across the source registers. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury such that there are eight BF16 data elements per register. Bradbury, as modified, has further taught: the predicate register to store at least eight predicate values (based on the explanation above, if there are eight BF16 elements in each register such that there would be eight parallel max operations, the predicate register would also have eight predicate values, one for each element pair, to individually control enabling/disabling for that pair) ; and each of the at least eight BF16 data elements of the first packed data operand corresponding to a different one of the at least eight BF16 data elements of the second packed data operand in a same data element position (such is the nature of vector compare instructions. Elements in the same positions are compared, i.e., from column 10, lines 28-32, “elements of the second operand…are compared to the corresponding…elements of the third operand”) , each of the predicate values corresponding to a different pair of corresponding BF16 data elements (again, if there are eight elements in each source register, then there are eight predicate values, to control the eight operations for the eight pairs (element 0 in the first source and element 0 in the second source being a first pair; element 1 in the first source and element 1 in the second source being a second pair; etc.) , wherein a BF16 data element of the first packed data operand has a sign bit, an 8-bit exponent, and a 7-bit fraction (see the 2 nd to last bit format on p.1 of Wikipedia) ; Bradbury, as modified, has further taught that the destination packed data operand is to include a corresponding data element that is a result of either a maximum comparison or a minimum comparison for each predicate value that is a first value (again, based on the explanation above, respective predicate elements will control corresponding maximum operations on element pairs from the source operands. When the predicate elements are a first value (e.g. 1), the operation will be performed, thereby generating a max result) , Bradbury has not taught for each predicate value that is a second value, the destination packed data operand is to include a corresponding data element that is either zero or remains unchanged . However, Official Notice is taken that setting a destination element to zero (zeroing masking) or leaving the current destination element unchanged (merging masking) when a predicate/mask indicates no operation is to be performed (i.e., a predicate element is set to a second value, e.g. 0) were well known in the art before applicant’s invention. The latter allows current results to be combined with previous results, for instance, so that results from different operations can be stored in a single register. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury such that for each predicate value that is a second value, the destination packed data operand is to include a corresponding data element that is either zero or remains unchanged. Referring to claim 2, Bradbury, as modified, has taught the processor of claim 1, wherein for said each predicate value that is the first value, the destination packed data operand is to include the corresponding data element that is the result of the maximum comparison of the pair of corresponding BF16 data elements (again, when a given predicate element is set to a first value, the operation is to be performed, and the operation in FIG.4A is a maximum operation which stores a result that is the maximum of the associated pair) . Referring to claim 3, Bradbury, as modified, has taught the processor of claim 1, wherein for said each predicate value that is the first value, the destination packed data operand is to include the corresponding data element that is the result of the minimum comparison of the pair of corresponding BF16 data elements (again, when a given predicate element is set to a first value, the operation is to be performed, and the operation in FIG.4K is a minimum operation which stores a result that is the minimum of the associated pair (also see FIG.3C and column 12, lines 26-33). Note from FIG.4K that, with the minimum instruction, when both elements in a compared pair are 0, the element from the second operand is stored (T(a))) . Referring to claim 4, Bradbury, as modified, has taught the processor of claim 1, wherein for said each predicate value that is the first value, when either one of the BF16 data elements of the pair of corresponding BF16 data elements is a NaN, the corresponding data element is to include the BF16 data element from the second packed data operand (again, when a given predicate element is set to a first value, the operation of FIG.4A is to be performed. When first operand (b) includes QNaN, the result is the element from the second operand (a), i.e., T(a)) . Referring to claim 5, Bradbury, as modified, has taught the processor of claim 1, wherein for said each predicate value that is the first value, when the BF16 data element of the pair of corresponding BF16 data elements from the first packed data operand is a NaN, the corresponding data element is to include the BF16 data element from the second packed data operand (again, when a given predicate element is set to a first value, the operation of FIG.4A is to be performed. When first operand (b) includes QNaN, the result is the element from the second operand (a), i.e., T(a)) . Referring to claim 6, Bradbury, as modified, has taught the processor of claim 1, wherein, for said each predicate value that is the second value, the destination packed data operand is to include the corresponding data element that remains unchanged (again, when a predicate values indicates “disabled”, the corresponding results element may remain unchanged by implementing merging masking) . Claim 7 is rejected for similar reasoning as claims 2, 4, and 6. Claim 8 is rejected for similar reasoning as claims 3, 4, and 6. Claim 9 corresponds to a method performed by the processor of claim 1. Thus, when all limitations of claim 9 are considered, claim 9 is firstly rejected for similar reasoning as claim 1. Alternatively, with respect to contingent limitations: Claim 9 is secondly rejected for similar reasoning as claim 1 except that the prior art does not need to teach the limitations in the 2 nd to last paragraph on p.3 (when the predicate entirely comprises second values); and Claim 9 is thirdly rejected for similar reasoning as claim 1 except that the prior art does not need to teach the limitations in the last paragraph on p.3 (when the predicate entirely comprises first values). Claims 10-15 are rejected for similar reasoning as claims 2-7, respectively, when all limitations are considered. Claims 10-15 are secondly rejected where their contingent limitations are not included as part of the claimed method. Thus, they would be rejected for a subset of reasoning set forth in the rejections of claims 9 and 2-7. Claim 16 corresponds to a medium with instructions that, when executed, cause a machine to perform the operation performed by the processor of claim 1. Thus, claim 16 is mostly rejected for similar reasoning as claim 1. Furthermore, Bradbury has taught a machine-readable storage medium storing instructions that when executed are to cause a machine to perform operations (see column 7, lines 10-19, column 21, lines 27-34 (cache), and column 18, line 61, to column 20, line 34). Regarding 112(f) interpretation of the machine, the examiner asserts that Bradbury is directed to a processor to perform the operations, including those corresponding to the instruction. While Bradbury has taught decode and execution circuits (FIG.1B, 122 and 124, respectively), Bradbury has not taught that these comprise a decode stage and execute stage of a pipeline, as interpreted under 112(f). However, Official Notice is taken that a pipeline including such states was well known in the art before applicant’s invention. A pipeline provides an alternative to slower serial execution by dividing instruction processing into stages such that performing different stages on different instructions in parallel is realized (e.g. while a first instruction is being executed in an execution stage, a second instruction is being decoded in a decode stage). This parallel form of execution is akin to an assembly line, which results in increased efficiency and throughput. As a result, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Bradbury such that decode 122 and execute 124 are decode and execution stages, respectively, in a pipeline. Claims 17-21 are rejected for similar reasoning set forth in the rejections of claims 2, 6, 4, 3, and 4, respectively. Referring to claim 22, Bradbury has taught an apparatus comprising: decode circuitry (FIG.1B, 122) to decode an instance of a single instruction (FIG.3A) , the single instruction to include fields for an opcode (FIG.3A, 302a) , an indication of a location of a first packed data source operand (FIG.3A, field 308 identifies first packed register V3, which may store multiple elements (column 10, lines 28-32)) , an indication of a location of a second packed data source operand (FIG.3A, field 306 identifies second packed register V2, which may store multiple elements (column 10, lines 28-32)) , and an indication of a packed data destination operand (FIG.3A, field 304 is a vector destination, which stores multiple results based on comparisons of multiple pairs of operations (FIG.4A)) , wherein the opcode is to indicate that execution circuitry (FIG.1B, 124) is to perform, for each data element position of the first and second packed data source operands, a maximum comparison of a floating-point data element at that data element position, and store a result of the maximum comparison into a corresponding data element position of the packed data destination operand (from FIG.4A and column 10, lines 28-35, a maximum operation is performed on each pair of elements in the source registers and the max result of the pair is stored to the target location corresponding to that pair) ; and the execution circuitry to execute the decoded instruction according to the opcode (again, the execute circuitry 124 in FIG.1B receives a decoded instruction from decode circuitry 122 and executes the maximum operation when a maximum opcode is detected). While Bradbury has taught that the instruction includes a field (M4) to configurably specify one of multiple different floating-point formats on which the maximum operation is to be performed (column 9, line 64, to column 10, line 7), Bradbury has not taught that one of those formats is BF16. However, Wikipedia has taught the BF16 format as one that specifically reduces storage requirements while preserving the dynamic range of FP32 (see the first paragraph). One of ordinary skill in the art would have recognized that all formats ultimately represent sequences of binary data, which may be compared the same way. As a result, in order to store less data to represent floating-point values, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury such that one of the selectable formats on which to perform a maximum operation includes BF16, such that each packed data operand includes multiple BF16 data elements . Claims 23-25 are rejected for similar reasoning set forth in the rejection of claims 1, 5, and 2, respectively. Referring to claim 26, Bradbury, as modified, has taught the apparatus of claim 22, wherein when the maximum comparison indicates other than a) that the data elements at that data element position of both source operands are both zero, b) that the data element of one source operand at that data element position is not-a-number, and c) that the data element at that data element position for the first source operand is larger than the corresponding data element at that data element position for the second source operand, the corresponding data element from the second source operand is stored at that data element position of the destination operand (from FIG.4A, this could correspond to the situation where both elements compared are negative infinity. In such a situation, none of (a), (b), and (c) are indicated, and the value from the second operand (T(a)) is stored to the appropriate destination position) . Referring to claim 27, Bradbury has taught an apparatus comprising: decode circuitry (FIG.1B, 122) to decode an instance of a single instruction (FIG.3C) , the single instruction to include fields for an opcode (FIG.3C, 322a) , an indication of a location of a first packed data source operand (FIG.3C, field 328 identifies first packed register V3, which may store multiple elements (column 12, lines 26-33)) , an indication of a location of a second packed data source operand (FIG.3C, field 326 identifies second packed register V2, which may store multiple elements (column 12, lines 26-33)) , and an indication of a packed data destination operand (FIG.3C, field 324 is a vector destination, which stores multiple results based on comparisons of multiple pairs of operations (FIG.4K)) , wherein the opcode is to indicate that execution circuitry (FIG.1B, 124) is to perform, for each data element position of the first and second packed data source operands, a maximum comparison of a floating-point data element at that data element position, and store a result of the maximum comparison into a corresponding data element position of the packed data destination operand (from FIG.4K and column 12, lines 26-33, a minimum operation is performed on each pair of elements in the source registers and the min result of the pair is stored to the target location corresponding to that pair) ; and the execution circuitry to execute the decoded instruction according to the opcode (again, the execute circuitry 124 in FIG.1B receives a decoded instruction from decode circuitry 122 and executes the minimum operation when a minimum opcode is detected). While Bradbury has taught that the instruction includes a field (M4) to configurably specify one of multiple different floating-point formats on which the minimum operation is to be performed (column 9, line 64, to column 10, line 7), Bradbury has not taught that one of those formats is BF16. However, Wikipedia has taught the BF16 format as one that specifically reduces storage requirements while preserving the dynamic range of FP32 (see the first paragraph). One of ordinary skill in the art would have recognized that all formats ultimately represent sequences of binary data, which may be compared the same way. As a result, in order to store less data to represent floating-point values, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bradbury such that one of the selectable formats on which to perform a minimum operation includes BF16, such that each packed data operand includes multiple BF16 data elements . Referring to claim 28, Bradbury, as modified, has taught the apparatus of claim 27, wherein, when the minimum comparison indicates that the data elements at that data element position of the source operands are both zero, the data element from the second source operand at that data element position is stored into a corresponding data element position of the destination operand (from FIG.4K, for some combinations of +0 and -0 operands, the result is T(a), which is the value from the second operand (a)) . Referring to claim 29, Bradbury, as modified, has taught the apparatus of claim 27, wherein, when the minimum comparison indicates that the data element of the first source operand at that data element position is not-a-number, the corresponding data element from the second source operand is stored at that data element position of the packed destination operand (from FIG.4K, when first operand (b) includes QNaN, the result is the element from the second operand (a), i.e., T(a)) . Referring to claim 30, Bradbury, as modified, has taught the apparatus of claim 27, wherein, when the minimum comparison indicates that the data element at that data element position for the first source operand is smaller than the corresponding data element at that data element position for the second source operand, the corresponding data element from the first source operand is stored at that data element position of the destination operand (again, see column 2, lines 26-33. A clear example from FIG.4K is when first operand (b) is -Fn and second operand (a) is +Fn. The former value is the lesser value and it (T(b)) is stored in the destination location) . Referring to claim 31, Bradbury, as modified, has taught the apparatus of claim 27, wherein when the minimum comparison indicates other than a) that the data elements at that data element position of both source operands are both zero, b) that the data element of one source operand at that data element position is not-a-number, and c) that the data element at that data element position for the first source operand is smaller than the corresponding data element at that data element position for the second source operand, the corresponding data element from the second source operand is stored at that data element position of the destination operand (from FIG.4K, this could correspond to the situation where both elements compared are negative infinity. In such a situation, none of (a), (b), and (c) are indicated, and the value from the second operand (T(a)) is stored to the appropriate destination position) . Conclusion 07-96 The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Intel, “Intel Architecture Software Developer’s Manual”, Volume 2 (1513 pages cited by applicant) has taught the MINPS instruction (p.3-517), which compares packed floating-point values and puts the lesser in the destination. When both source elements are 0, or when either is SNAN, the value from the second source is stored to the destination. A MAXPS instruction is also disclosed (p.3-508). This document is particularly relevant to the claims. Gogar (US 2020/0104132) has taught max circuitry to find the max among pairs of elements from two packed source registers and store it into a packed result (e.g. FIG.1A). Desai (US 2003/0167460) has taught a vector max/min instruction in FIG.13 that operates on packed data. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David J. Huisman/Primary Examiner, Art Unit 2183 Application/Control Number: 18/436,982 Page 2 Art Unit: 2183 Application/Control Number: 18/436,982 Page 3 Art Unit: 2183 Application/Control Number: 18/436,982 Page 4 Art Unit: 2183 Application/Control Number: 18/436,982 Page 5 Art Unit: 2183 Application/Control Number: 18/436,982 Page 6 Art Unit: 2183 Application/Control Number: 18/436,982 Page 7 Art Unit: 2183 Application/Control Number: 18/436,982 Page 8 Art Unit: 2183 Application/Control Number: 18/436,982 Page 9 Art Unit: 2183 Application/Control Number: 18/436,982 Page 10 Art Unit: 2183 Application/Control Number: 18/436,982 Page 11 Art Unit: 2183 Application/Control Number: 18/436,982 Page 12 Art Unit: 2183 Application/Control Number: 18/436,982 Page 13 Art Unit: 2183 Application/Control Number: 18/436,982 Page 14 Art Unit: 2183 Application/Control Number: 18/436,982 Page 15 Art Unit: 2183 Application/Control Number: 18/436,982 Page 16 Art Unit: 2183 Application/Control Number: 18/436,982 Page 17 Art Unit: 2183 Application/Control Number: 18/436,982 Page 18 Art Unit: 2183 Application/Control Number: 18/436,982 Page 19 Art Unit: 2183 Application/Control Number: 18/436,982 Page 20 Art Unit: 2183 Application/Control Number: 18/436,982 Page 21 Art Unit: 2183 Application/Control Number: 18/436,982 Page 22 Art Unit: 2183 Application/Control Number: 18/436,982 Page 23 Art Unit: 2183 Application/Control Number: 18/436,982 Page 24 Art Unit: 2183 Application/Control Number: 18/436,982 Page 25 Art Unit: 2183 Application/Control Number: 18/436,982 Page 26 Art Unit: 2183 Application/Control Number: 18/436,982 Page 27 Art Unit: 2183 Application/Control Number: 18/436,982 Page 28 Art Unit: 2183 Application/Control Number: 18/436,982 Page 29 Art Unit: 2183 Application/Control Number: 18/436,982 Page 30 Art Unit: 2183 Application/Control Number: 18/436,982 Page 31 Art Unit: 2183 Application/Control Number: 18/436,982 Page 32 Art Unit: 2183 Application/Control Number: 18/436,982 Page 33 Art Unit: 2183 Application/Control Number: 18/436,982 Page 34 Art Unit: 2183
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