DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Embodiment 1 (Claims 1-10, 18-20 readable thereon) in the reply filed on July 22,2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fillion et al (USPGPUB 20100132994, hereinafter “Fillion”).
Regarding Claim 18, Fillion teaches (Figs. 5-16) a method of manufacturing a semiconductor package, the method comprising: forming a first photoresist layer on a first insulating layer (214); forming a first photoresist pattern having first opening patterns using a first exposure mask (as seen in Figs. 5-16 of Fillion, openings 216, 218 are formed in the first insulating layer, and the use of a photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure); etching the first insulating layer using the first photoresist pattern as a first etching mask to form first via holes (216, 218) ; removing the first photoresist pattern; forming a second photoresist layer on the first insulating layer (214); forming a second photoresist pattern having second opening patterns using a second exposure mask (as seen in Figs. 5-16 of Fillion, openings 232, 234 are formed in the first insulating layer, and these openings are different in dimensions than that of holes 216, 218. The use of a second photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure); etching the first insulating layer using the second photoresist pattern as a second etching mask to form second via holes (232, 234); removing the first photoresist pattern; forming a redistribution wiring layer on the first insulating layer (Fig. 16, conductive elements 322 would be part of the first wiring layer), the redistribution wiring layer having first redistribution wirings that are electrically connected to first bonding pads (244 as seen in Fig. 10) under (note that the chip is seen on the bottom of the figure, but redistribution wiring pads are seen over the device, and as such, this type of device is often used in an orientation inverted from how it is manufactured) the first insulating layer through the first via hole and the second via hole; and mounting a semiconductor chip (Fig. 5, 204) on the redistribution wiring layer, the semiconductor chip comprising chip pads electrically connected to (redistribution wirings are seen connected to pads 206, 208, 210, 212 which are directly in contact with and attached to chip 204) the first redistribution wirings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (USPGPUB 20090224391, hereinafter “Lin”) in view of Fillion.
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Regarding Claim 1, Lin teaches (Fig. 11) a method of manufacturing a semiconductor package, the method comprising: forming a plurality of lower redistribution wiring layers (LRW) comprising first redistribution wirings stacked in at least two layers (lower redistribution wiring layers is seen containing a plurality of layers of first redistribution wirings, hereinafter 1RW, containing conductive elements 82, 88, 86, 84, 90) of the plurality of lower redistribution wiring layers (LRW); mounting a semiconductor chip (102) on the plurality of lower redistribution wiring layers (LRW), the semiconductor chip (102) comprising chip pads (122) that are electrically connected to the first redistribution wirings (1RW); forming a sealing member (106) covering the semiconductor chip (102) on the plurality of lower redistribution wiring layers (LRW); forming a plurality of through-vias (100) penetrating the (through-vias 100 are seen penetrating sealing member 106) sealing member (106), the plurality of through-vias (100) being electrically connected to the first redistribution wirings (1RW); and forming a plurality of upper redistribution wiring layers (URW) on the sealing member (106), the plurality of upper redistribution wiring layers (URW) comprising second redistribution wirings (redistribution wirings 108, 110, 112, 114, hereinafter 2RW) electrically connected to the plurality of through-vias (100),
Lin is silent with regards to a method wherein the forming the plurality of lower redistribution wiring layers comprises: forming a first insulating layer; performing a first photo etching process on the first insulating layer to form first via holes; performing a second photo etching process on the first insulating layer to form second via holes; and forming first lower redistribution wirings on the first insulating layer, the first lower redistribution wirings being electrically connected to first bonding pads under the first insulating layer through the first via hole and the second via hole.
Fillion teaches (Figs. 5-16) a method wherein the forming the plurality of lower redistribution wiring layers comprises: forming a first insulating layer (214); performing a first photo etching process (as seen in Figs. 5-16 of Fillion, openings 216, 218 are formed in the first insulating layer, and the use of a photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure) on the first insulating layer (214)to form first via holes (216, 218); performing a second photo etching process (as seen in Figs. 5-16 of Fillion, openings 323, 324 are formed in the first insulating layer, and these openings are different in dimensions than that of holes 216, 218. The use of a second photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure) on the first insulating layer (214) to form second via holes (232, 234); and forming first lower redistribution wirings on the first insulating layer (Fig. 16, conductive elements 322 would be part of the first wiring layer), the first lower redistribution wirings being electrically connected to first bonding pads (244 as seen in Fig. 10) under the first insulating layer (214) through the first via hole and the second via hole.
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the etching and fabrication steps of Fillion into the device of Lin in order to arrive at the expected result of creating a method with the known benefit of allowing for mass-production with reasonable expectation of success.
Regarding Claim 4, Lin in view of Fillion teaches (Fillion Figs. 5-16) the method of claim 1, wherein the performing the first photo etching process on the first insulating layer (Fillion 214) comprises: forming a first photoresist layer on the first insulating layer (Fillion 214); performing an exposure process on the first photoresist layer using a first exposure mask (as seen in Figs. 5-16 of Fillion, openings 216, 218 are formed in the first insulating layer, and the use of a photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure); performing a development process to form a first photoresist pattern having first opening patterns corresponding to the first via holes (Fillion 216, 218); etching the first insulating layer using the first photoresist pattern as a first etching mask to form the first via holes (Fillion 216, 218); and removing the first photoresist pattern.
Regarding Claim 5, Lin in view of Fillion teaches (Fillion Figs. 5-16) the method of claim 4, wherein the etching the first insulating layer (Fillion 214) to form the first via holes (Fillion 216, 218) comprises performing an isotropic etching process (the photo etching process would be understood as isotropic as it would be carried out in batches for larger scale productions, as would be obvious to one of ordinary skill in the art) using the first photoresist pattern as the first etching mask on the first insulating layer (Fillion 214).
Regarding Claim 6, Lin in view of Fillion teaches (Fillion Figs. 5-16) the method of claim 1, wherein the performing the second photo etching process on the first insulating layer (Fillion 214) comprises: forming a second photoresist layer on the first insulating layer (Fillion 214); performing an exposure process on the second photoresist layer using a second exposure mask (as seen in Figs. 5-16 of Fillion, second openings 232, 234 are formed in the first insulating layer, and the use of a photomask process with gaps for exposure, and then removing the structure after the fact, to achieve this is understood to be inherent to manufacturing this structure); and performing a development process to form a second photoresist pattern having second opening patterns corresponding to the second via holes; etching the first insulating layer using the second photoresist pattern as a second etching mask to form the second via holes; and removing the second photoresist pattern.
Regarding Claim 7, Lin in view of Fillion teaches (Fillion 216, 218) the method of claim 6, wherein etching the first insulating layer (Fillion 214) to form the second via holes (232, 234 of Fillion) comprises performing an isotropic etching process (the photo etching process would be understood as isotropic as it would be carried out in batches for larger scale productions, as would be obvious to one of ordinary skill in the art) using the second photoresist pattern as the second etching mask on the first insulating layer (Fillion 214).
Regarding Claim 8, Lin in view of Fillion teaches the method of claim 1, wherein at least one sidewall of the first via hole and the second via hole (Fillion 232, 234; ) has an angle range of 85 degrees to 105 degrees (Lin Fig. 11, the vias are seen having a substantially right angle with the bottom surfaces of the insulating layer they are disposed about)) with respect to a lower surface of the first insulating layer (Fillion 214).
Regarding Claim 10, Lin in view of Fillion teaches (Lin Fig. 11) the method of claim 1, wherein the forming the plurality of upper redistribution wiring layers (URW of Lin) comprises: forming a second insulating layer; performing a third photo etching process on the second insulating layer to form third via holes; performing a fourth photo etching process on a third insulating layer to form fourth via holes; and forming first upper redistribution wirings on the second insulating layer, the first upper redistribution wirings being electrically connected to second bonding pads under the second insulating layer through the third via hole and the fourth via hole (the upper redistribution wiring layers URW of Lin are seen having two differently sized holes, similar in manner to that of the lower redistribution wirings LRW of Lin, and as such, similarly, it would be obvious to a person of ordinary skill in the art to incorporate a masking process of two differently-sized photomasks, transferring openings into a set of via holes, and then removing the photomask structure to create the via layout).
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Fillion as applied to Claim 1 above, and further in view of Sawamoto et al (USPGPUB 20220155681, hereinafter “Sawamoto”).
Regarding Claim 2, Lin in view of Fillion teaches the method of claim 1, but is silent with regards to a method wherein the first insulating layer comprises a photosensitive insulating material.
Sawamoto teaches a method wherein the first insulating layer comprises a photosensitive insulating material ([0013], “a photosensitive resin composition for interlayer insulating layer, each of which is excellent in both photosensitive characteristics and strippability from a support film”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the photosensitive resin of Sawamoto into the method of Lin in view of Fillion in order to arrive at the expected result of creating a device using with improved insulating capability (see [0030] of Sawamoto) with reasonable expectation of success.
Regarding Claim 3, Lin in view of Fillion and in further view of Sawamoto teaches the method of claim 2, wherein the forming the first insulating layer comprises: coating a photosensitive insulating material layer of the first insulating layer; and performing a curing process on the photosensitive insulating material layer (Sawamoto [0005], “the laser processing is the mainstream as a method for forming a via in the interlayer insulating layer formed upon curing the thermosetting resin film”)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Fillion as applied to claim 1 above, and further in view of Ecton et al (USPGPUB 20190304912 , hereinafter “Ecton”).
Regarding Claim 9, Lin in view of Fillion teaches the method of claim 1, but is silent with regards to a method wherein at least one of the first via hole and the second via hole has a diameter of 1 μm to 8 μm
Ecton teaches a method wherein at least one of the first via hole and the second via hole has a diameter of 1 μm to 8 μm ([0025], “The via structures have a tapered profile characteristic of a subtractive etch process. The via structures provide a space to thickness ratio of greater than 2:1, in some cases. The via structures described herein may have diameters of 10 microns or less”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Ecton into the method of Lin in view of Fillion in order to arrive at the expected result of creating a method of manufacture for a device which is with reasonable expectation of success.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fillion as applied to claim 18 above, and further in view of Sawamoto.
Regarding Claim 19, Fillion teaches the method of claim 18, but is silent with regards to a method wherein the first insulating layer comprises a photosensitive insulating material.
Sawamoto teaches a method wherein the first insulating layer comprises a photosensitive insulating material ([0013], “a photosensitive resin composition for interlayer insulating layer, each of which is excellent in both photosensitive characteristics and strippability from a support film”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the photosensitive resin of Sawamoto into the method of Fillion in order to arrive at the expected result of creating a device using with improved insulating capability (see [0030] of Sawamoto) with reasonable expectation of success.
Regarding Claim 20, Fillion in view of Sawamoto teaches the method of claim 19, wherein the forming the first insulating layer comprises: coating a photosensitive insulating material layer of the first insulating layer; and performing a curing process on the photosensitive insulating material layer (Sawamoto [0005], “the laser processing is the mainstream as a method for forming a via in the interlayer insulating layer formed upon curing the thermosetting resin film”) .
Conclusion
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/V.J.L./Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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