DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the plurality of conductive electrodes". There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution the examiner provisionally interprets the limitation as "the conductive layer comprises a plurality of conductive electrodes that"
Election/Restrictions
Applicant’s election without traverse of Species A (claims 1-2, 4-6, 8-9, 18-20, and 22) in the reply filed on 5-26-2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8-9, 18-20, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maruyama (US 2017/0278916).
[claim 1] A display apparatus (fig. 4) comprising a display area (DR, fig. 4) and a peripheral area (PR, fig. 4), the display apparatus comprising: a first thin-film transistor (TFT1, fig. 4) in the peripheral area, and comprising a silicon semiconductor layer (CH1 of TFT1 is made of polysilicon [0025], note also same layer CL1 made of polysilicon [0029]); a second thin-film transistor (TFT2 above CL2, SW2 fig. 4) in the display area, and comprising an oxide semiconductor layer (CH2 of TFT2 is made of semiconductor oxide [0026]) over the silicon semiconductor layer; and a semiconductor pattern (CL1 made of polysilicon [0029] is the same layer the semiconductor layer of TFT1 [0029]) in the display area at the same layer as that of the silicon semiconductor layer of the first thin-film transistor [0029].
[claim 2] The display apparatus of claim 1, wherein the semiconductor pattern comprises a silicon semiconductor [0029].
[claim 4] The display apparatus of claim 1, further comprising: a conductive layer (CL2, fig. 4), overlapping with the semiconductor pattern; and signal lines (e.g. CP1 and CP2 connected to CL1 or CH1 of TFT1, fig. 4)) electrically connected to opposite ends of the semiconductor pattern not overlapping with the conductive layer, wherein the signal lines are electrically connected to the conductive layer (fig. 4).
[claim 5] The display apparatus of claim 4, wherein the conductive layer is at the same layer as that of a gate electrode of the first thin-film transistor (CL2 is the same layer as GE1 which is the gate electrode of TFT1, fig. 4, [0030]).
[claim 6] The display apparatus of claim 4, wherein the oxide semiconductor layer of the second thin-film transistor overlaps with the semiconductor pattern (fig. 4).
[claim 8] The display apparatus of claim 7, wherein the conductive layer comprises a plurality of conductive electrodes (the two layers of CL1, fig. 4) that are at the same layer as that of a gate electrode of the first thin-film transistor (fig. 4, [0029]).
[claim 9] The display apparatus of claim 7, wherein the oxide semiconductor layer of the second thin-film transistor overlaps with the semiconductor pattern (fig. 4).
[claim 18] The display apparatus of claim 1, further comprising a third thin-film transistor (TFT2 not above CL2, SW1, fig. 4) in the display area, and comprising an oxide semiconductor layer (CH2 of TFT2 is made of semiconductor oxide [0026]) over the silicon semiconductor layer, wherein the semiconductor pattern is configured to electrically connect the oxide semiconductor layer of the second thin-film transistor to the oxide semiconductor layer of the third thin-film transistor (the two TFT2’s correspond to SW1 and SW2 are interconnected in fig. 3 via the capacitor, fig. 4).
[claim 19] A display apparatus (fig. 4) comprising a display area (DR, fig. 4) and a peripheral area (PR, fig. 4), the display apparatus comprising: a semiconductor pattern (CL1 made of polysilicon [0029] is the same layer the semiconductor layer of TFT1 [0029]) in the display area; a conductive layer (CL2, fig. 4) on the semiconductor pattern, and overlapping with the semiconductor pattern; a first electrode layer (CL2, fig. 4) on the conductive layer, and overlapping with the conductive layer; an oxide semiconductor layer (CH2 of TFT2, SW2 is made of semiconductor oxide [0026]) on the first electrode layer; a second electrode layer (GE2, fig. 4) on the oxide semiconductor layer; and a third electrode layer (18, fig. 4) on the second electrode layer, and overlapping with the second electrode layer.
[claim 20] The display apparatus of claim 19, wherein the semiconductor pattern comprises a silicon semiconductor [0029].
[claim 22] The display apparatus of claim 19, further comprising: a silicon semiconductor layer (CH1 of TFT1, fig. 4, [0025]) in the peripheral area; and a fourth electrode layer (GE, fig. 4) on the silicon semiconductor layer, and overlapping with the silicon semiconductor layer, wherein the silicon semiconductor layer is at the same layer as that of the semiconductor pattern [0029], and wherein the fourth electrode layer is at the same layer as that of the conductive layer [0030].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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