DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 12 August 2026. Claims 1-6, 9-16, 19-24 are pending in this application. Claims 7-8, 17-18 are cancelled, and Claims 21-24 are newly added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 6 in the reply filed on 12 August 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Lo (US 2023/0018031 A1)
Regarding Claim 9, Lo discloses (as shown in Fig. 2) A package structure ([0042] FIG. 1 illustrates a top view of a package structure 3), comprising:
a terminal; ([0083] The package structure 3 may be electrically connected to the first circuit layer 41 of the base substrate 40 through the solder materials 36)
an upper pad adjacent ([0053] first electrical contact 205) to a top surface of the terminal (36); (See fig. 3, showing the first electrical contact on top of the redistribution layers that are part of the terminal)
and a first solder ([0057] at least one first reflowable material 35) disposed over the upper pad (205), (See Fig. 4, showing first reflowable material 37 on the first electrical contact 205)
and free from contacting a lateral surface of the upper pad (205), (See Fig. 4)
wherein the upper pad is configured to prevent the first solder from lateral bleeding.
Claim interpretation note: the limitation “wherein the upper pad is configured to prevent the first solder from lateral bleeding.” is a functional limitation. Functional claim language that is not limited to a specific structure covers all devices that are capable of performing the recited function. Therefore, if the prior art discloses a device that can inherently perform the claimed function, a rejection under 35 USC 102 and/or 35 USC 103 may be appropriate. (MPEP 2114) As shown in Fig. 4, there is no lateral bleeding of the first reflowable material 37.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Lo (US 2023/0018031 A1) and further in view of Liu et. al (US 2006/0244115 A1).
Regarding Claim 1, Lo discloses (as shown in Fig. 2) A package structure ([0042] FIG. 1 illustrates a top view of a package structure 3), comprising:
an electronic device ([0051] The first electronic device 24);
wherein the electronic device (24) includes at least one via ([0052] at least one first bump 25) (See Fig. 4A, showing the bump 25 acts as a via through the passivation layer 244) protruding from a bottom surface of the electronic device (24). (See Fig. 4A, showing the bump 25 protruding from the bottom of the passivation layer 244)
However, Lo fails to disclose:
a lead frame;
an electronic device disposed adjacent to the lead frame;
and a level-maintaining structure disposed between the electronic device and the lead frame, and configured to prevent the electronic device from tilting with respect to the lead frame,
Liu discloses (as shown in Fig. 2)
a lead frame ([0021] a lead frame 200);
an electronic device ([0021] a chip 210) disposed adjacent to the lead frame (200); (See Fig. 3, showing the chip 210 on the lead frame 200)
and a level-maintaining structure ([0024] bonding bumps 212) disposed between the electronic device (210) and the lead frame (200), (See Fig. 3)
and configured to prevent the electronic device (210) from tilting with respect to the lead frame (200),
Claim interpretation note: the limitation “configured to prevent the electronic device from tilting with respect to the lead frame” is a functional limitation. Functional claim language that is not limited to a specific structure covers all devices that are capable of performing the recited function. Therefore, if the prior art discloses a device that can inherently perform the claimed function, a rejection under 35 USC 102 and/or 35 USC 103 may be appropriate. (MPEP 2114) Bumps are capable of performing the function of preventing tilt.
Liu teaches that the lead frame has a heat-sinking function. ([0005] In some package structures, the chip pad 106 also has a heat-sinking function, so that the chip pad 106 may be referred to a heat-sinking pad) Therefore, it would have been obvious to combine the lead frame of Liu with the electronic device and bonding structure of Lo in order to dissipate heat.
Alternatively, Claim 1 can be rejected under 35 USC 103 as being unpatentable over Lo (US 2023/0018031 A1) and further in view of Liu et. al (US 2006/0244115 A1) and further in view of Yun et. al (Us 2024/0145418 A1)
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Lo (US 2023/0018031 A1) and further in view of Liu et. al (US 2006/0244115 A1) and further in view of Yun et. al (Us 2024/0145418 A1).
Regarding Claim 1, Lo discloses (as shown in Fig. 2) A package structure ([0042] FIG. 1 illustrates a top view of a package structure 3), comprising:
an electronic device ([0051] The first electronic device 24);
wherein the electronic device (24) includes at least one via ([0052] at least one first bump 25) (See Fig. 4A, showing the bump 25 acts as a via through the passivation layer 244) protruding from a bottom surface of the electronic device (24). See Fig. 4A, showing the bump 25 protruding from the bottom of the passivation layer 244)
However, Lo fails to disclose:
a lead frame;
an electronic device disposed adjacent to the lead frame;
and a level-maintaining structure disposed between the electronic device and the lead frame, and configured to prevent the electronic device from tilting with respect to the lead frame.
Liu discloses (as shown in Fig. 2)
a lead frame ([0021] a lead frame 200);
an electronic device ([0021] a chip 210) disposed adjacent to the lead frame (200); (See Fig. 3, showing the chip 210 on the lead frame 200)
Liu teaches that the lead frame has a heat-sinking function. ([0005] In some package structures, the chip pad 106 also has a heat-sinking function, so that the chip pad 106 may be referred to a heat-sinking pad) Therefore, it would have been obvious to combine the lead frame of Lin with the electronic device and bonding structure of Lo in order to dissipate heat.
However, Liu fails to disclose a level-maintaining structure disposed between the electronic device and the lead frame, and configured to prevent the electronic device from tilting with respect to the lead frame,
Yun discloses (as shown in Fig. 1) a level-maintaining structure ([0046] The support post 210) disposed between the electronic device ([0027] semiconductor chip 300) and the redistribution structure ([0027] redistribution structure 100), ([0046] The support post 210 and the conductive filler 220 may be interposed between the semiconductor chip 300 and the plurality of upper connection pads 150A and 150B of the redistribution structure 100)
and configured to prevent the electronic device (300) from tilting with respect to the redistribution structure (100) ([0051] The support post 210 may be connected to the first upper connection pad 150A. The second post 212 forming the support post 210 may contact the bottom surface of the semiconductor chip 300. The second post 212 may support the semiconductor chip 300 and contact the bottom surface of the semiconductor chip 300.)
Claim interpretation note: the limitation “configured to prevent the electronic device from tilting with respect to the lead frame” is a functional limitation. Functional claim language that is not limited to a specific structure covers all devices that are capable of performing the recited function. Therefore, if the prior art discloses a device that can inherently perform the claimed function, a rejection under 35 USC 102 and/or 35 USC 103 may be appropriate. (MPEP 2114) Support posts are capable of performing the function of preventing tilt.
Yun teaches that the support posts support the semiconductor chip ([0051] The support post 210 may be connected to the first upper connection pad 150A. The second post 212 forming the support post 210 may contact the bottom surface of the semiconductor chip 300. The second post 212 may support the semiconductor chip 300 and contact the bottom surface of the semiconductor chip 300.) Therefore, it would have been obvious to combine the support posts of Yun with the electronic device, bonding structure, and lead frame of Lo in view of Liu in order to support the semiconductor device.
Since the bonding in Lo in view of Liu would be between the semiconductor device and the lead frame, it would be obvious for the support posts of Yun to be disposed between the electronic device and lead frame, since the support posts are part of the bonding structure for the semiconductor chip. ([0063] In the semiconductor package 1 according to the disclosure, the semiconductor chip 300 may be supported by the support post 210 to form bonding of the semiconductor chip 300.)
Regarding Claim 6, Lo discloses (as shown in Fig. 2, 4) wherein the level-maintaining structure is disposed under the electronic device ([0052] Further, the first electronic device 24), and includes a solder material, ([0053] the first reflowable material 35 and the second reflowable material 37 may be solder materials) (See Fig. 4, showing the bump 25 and the solder 35 under the first electronic device 24)
wherein the package structure further comprises a pad ([0060] first conductive pad 245 ) disposed between the solder material (35) and the electronic device (24), (See Fig. 4, showing the first conductive pad 245 between the solder 35 and the first electronic device 24)
and configured to adjust a thickness of the solder material. ([0073] That is, the first accommodation space 257 may be configured to reduce the difference between a first elevation of the first reflowable material 35 and a second elevation of the second reflowable material 37 after a reflowing process.)
However, Lo fails to disclose the pad is a dummy pad.
Yun discloses (as shown in Fig. 1) wherein the support posts (210) are dummy posts. ([0071] Thus, the first post 211 may not serve to transmit an electric signal.) ([0072] The passivation layer 350 may include an insulation material, such that the support post 210 may not be electrically connected to the semiconductor chip 300.)
Lo teaches that the structure of the pillars helps to reduce elevation differences. (([0073] That is, the first accommodation space 257 may be configured to reduce the difference between a first elevation of the first reflowable material 35 and a second elevation of the second reflowable material 37 after a reflowing process.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the support posts From Yun have the design of the pillars in Lo in order to reduce elevation differences. Since the support posts in Yun are not electrically connected to the semiconductor device, this would make the pads of the combination of Lo and Yun dummy pads.
Claim(s) 2, 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo in view of Liu and Pendse as applied to claim 1 above, and further in view of Pendse (US 2012/0241984 A1).
Regarding Claim 2, Lo further discloses (as shown in Fig. 4) wherein the at least one via includes a plurality of vias having inconsistent gaps between adjacent vias. (See Fig. 4)
Lo in view of Liu and Yun fails to disclose wherein the at least one via configured to transmit noise current.
Claim interpretation note: “configured to transmit noise current“ is a functional limitation. Functional claim language that is not limited to a specific structure covers all devices that are capable of performing the recited function. Therefore, if the prior art discloses a device that can inherently perform the claimed function, a rejection under 35 USC 102 and/or 35 USC 103 may be appropriate. (MPEP 2114)
Pendse discloses (as shown in fig. 5, 7) wherein the at least one is configured to transmit noise current ([0074] Generally, ground lines in package substrates are preferably separated from signal lines by distances comparable to at least of the same order of magnitude as the distances between adjacent signal lines, so that field lines generated by signals go to ground rather than interfering with other signals.)
Pendse teaches that the ground lines prevent the field lines from interfering with other signals. ([0074] Generally, ground lines in package substrates are preferably separated from signal lines by distances comparable to at least of the same order of magnitude as the distances between adjacent signal lines, so that field lines generated by signals go to ground rather than interfering with other signals.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include ground lines as in Pendse in order to prevent the field lines from interfering with other signals.
Regarding Claim 4, Lo further discloses (as shown in Fig. 2, 4) wherein the electronic device includes a high- density region and a low-density region, (See An. Fig. 2 below)
a distribution density of the plurality of vias in the high- density region is greater than a distribution density of the plurality of vias in the low-density region, (See An. Fig. 2 below)
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Yun further teaches (as shown in Fig. 2B) wherein the level-maintaining structure is disposed under the low-density region. (See Fig. 2B showing support posts 210 in areas lacking conductive fillers 220)
Regarding Claim 5, Yun further discloses the at least one via includes a dummy via ([0037] Among the plurality of upper connection pads 150A and 150B, a plurality of first upper connection pads 150A may be or may not be electrically connected to the redistribution pattern 110. It is shown in FIG. 1 that the plurality of first upper connection pads 150A is not connected to the redistribution pattern 110.)
Lo further discloses (as shown in Fig. 2) the level-maintaining structure includes a protrusion portion of the dummy via protruding from a bottom surface of the electronic device (24). (See Fig. 4A, showing the bump 25 acts as a via through the passivation layer 244) protruding from a bottom surface of the electronic device (24). (See Fig. 4A, showing the bump 25 protruding from the bottom of the passivation layer 244)
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo in view of Liu, Yun, and Pendse as applied to claim 2 above, and further in view of Carrazzone et. al (US 2024/0243087 A1) in view of Wang (Us 2012/0153459 A1).
Regarding Claim 3, Lo further discloses (as shown in fig. 2) wherein the plurality of vias includes a first via having a first width and a second via having a second width, wherein the first width and the second width are different from each other. ([0090] The second bump 27 has a width less than a width of the first bump 25)
However, Lo fails to disclose the plurality of vias includes a third via having a third width that is different from the first width and second width.
Carrazzone discloses (as shown in Fig. 2) wherein the plurality of vias ([0019] metal vias 225) includes a first via having a first width, a second via ([0019] metal vias 227) having a second width, and a third via ([0019] metal vias 229) having a third width, wherein the first width, the second width and the third width are different from each other. ([0026] Specifically, in this example, the solder resist openings 602 include three different widths 606, 608, 610 that define the resulting widths of the metal vias 225, 227, 229 associated with the different bumps 202, 204, 206.)
Wang teaches that the different areas of the semiconductor die have different densities of devices. ([0031] according to different densities of semiconductor devices moving toward the edge) Wang further teaches that the size of the bonding pads are changed in each of these regions with different densities of devices. ([0031] In a third embodiment, as FIG. 2 shows, when a chip size is 8 mm, taking a central point 10 of the chip as a center, according to different densities of semiconductor devices moving toward the edge, the chip is divided into a first region 100, a second region 102 and a third region 104. The sizes of the contact bonding pads are changed, so are the sizes of the bumps on the contact bonding pads.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have three different sized vias as in Carrazzone in order to correspond to three areas of the device with different densities.
Claim(s) 19-20, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et. al (US 2024/0379479 A1) in view of Wang (Us 2012/0153459 A1).
Regarding Claim 19, Lin discloses (as shown in Fig. 11a) A package structure ([0069] FIG. 11b illustrates electronic device 310 including PCB 312 with a plurality of semiconductor packages mounted on a surface of the PCB, including semiconductor package 170) and comprising:
including a center region, a periphery region and an intermediate region therebetween from a top view,
an electronic device ([0072] semiconductor die 104 with electrical components 130) disposed in the center region and the intermediate region; (See An. Fig. 11a, showing the semiconductor die 104 is in the center and intermediate regions)
a redistribution structure ([0068] build-up interconnect structure 180) disposed under the electronic device (104); (See Fig. 11a)
a carrier disposed ([0068] a printed circuit board (PCB) or other substrate 312) under the redistribution structure (180); (See Fig. 11a)
at least one first pad ([0057] contact pads 188) disposed at a contact area between the redistribution structure (180) and the carrier (312) and in the center region; (See An. Fig. 11a, showing a contact pad in the center region)
and at least one second pad ([0057] contact pads 188)disposed at the contact area between the redistribution structure (180) and the carrier (312) and in the intermediate region, (See An. Fig. 11a, showing a contact pad in the intermediate region)
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However, Lin fails to disclose:
wherein a width of the at least one first pad is different from a width of the at least one second pad, the at least one first pad is configured to transmit noise current, and the at least one second pad is configured to transmit signals.
Wang discloses (as shown in Fig. 6)
including a center region ([0035] a first region I), a periphery region ([0035] a third region III) and an intermediate region ([0035] a second region II) therebetween from a top view, (See Fig. 6)
wherein a width of the at least one first pad ([0043] contact bonding pads 406a) is different from a width of the at least one second pad ([0043] contact bonding pads … 406b), ([0031] However, the diameters of the bumps are quite different) (See Fig. 6, showing the contact bonding pads 406a and 406b are different sizes)
the at least one first pad is configured to transmit noise current, and the at least one second pad is configured to transmit signals.
Claim interpretation note: “configured to transmit noise current“ and “configured to transmit signals” are functional limitation. Functional claim language that is not limited to a specific structure covers all devices that are capable of performing the recited function. Therefore, if the prior art discloses a device that can inherently perform the claimed function, a rejection under 35 USC 102 and/or 35 USC 103 may be appropriate. (MPEP 2114)
Wang teaches that the different areas of the semiconductor die have different densities of devices. ([0031] according to different densities of semiconductor devices moving toward the edge) Wang further teaches that the size of the bonding pads are changed in each of these regions with different densities of devices. ([0031] In a third embodiment, as FIG. 2 shows, when a chip size is 8 mm, taking a central point 10 of the chip as a center, according to different densities of semiconductor devices moving toward the edge, the chip is divided into a first region 100, a second region 102 and a third region 104. The sizes of the contact bonding pads are changed, so are the sizes of the bumps on the contact bonding pads.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have three different sized vias as in Wang in order to correspond to three areas of the device with different densities.
Regarding Claim 20, Wang furth discloses (as shown in Fig. 6) wherein the at least one first pad (406a) includes a plurality of first pads, (See Fig. 6, showing 2 contact bonding pads 406a)
the at least one second pad (406b) includes a plurality of second pads, (See Fig. 4, showing 2 contact bonding pads 406b)
wherein a pitch of two adjacent ones of the plurality of first pads (406a) is less than a pitch of two adjacent ones of the plurality of second pads (406b). (See An. Fig. 6 below)
Claim Interpretation Note: Under BRI, the limitation “a pitch of two adjacent ones of the plurality of second pads” only means the pitch between the 2 closest second pads. It does not require the second pads to not have other pads between them.
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Regarding Claim 22, Wang further discloses (as shown in Fig. 6) at least one first solder ([0046] bumps 408a) disposed on the at least one first pad (406a); and at least one second solder ([0046] bumps 408b) disposed on the at least one second pad (406b), ([0046] As FIG. 6 shows, the bumps 408a, 408b and 408c are respectively formed on each of the contact bonding pads 406a, 406b and 406c.)
wherein a width of the second solder (408b) is less than a width of the first solder (408a), ([0031] However, the diameters of the bumps are quite different) (See Fig. 6)
wherein the second solder (408b) is closer to a periphery edge of the carrier (312) than the first solder (408a) is. (See Fig. 6)
Allowable Subject Matter
Claim 10-16, 21, 23-24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, Lo fails to disclose a second solder contacting a top surface of a lead frame.
The closest prior art is Heo et. al (US 2020/002638 A1). Heo discloses (as shown in Fig. 12) where the solder ([0095] The electrical connection structure 195 may be formed of multiple layers or a single layer. In the case of a multi-layered structure, it may include a copper pillar and a solder) extends around the pad ([0103] A backside wiring layer 162) (See Fig. 12)
However, Heo does not disclose a combination of solders, some of which do not extend around the pad and some of which do. It would not be obvious to combine the prior art to have a combination of solders, some of which do not extend around the pad and some of which do.
Regarding Claims 11-15, Claims 11-15 depend from Claim 10 and contain allowable subject matter for the same reasons.
Regarding Claim 16, Lo fails to disclose a lead tapering, and having a contact surface and a lower surface outside the contact surface, wherein the lower surface extends from a thicker end to a thinner end;
and a solder mask disposed on the lower surface and exposing a portion of the lower surface, wherein the solder mask partially covers an encapsulant, wherein the solder mask tapers toward the contact surface.
Other relevant Prior art is Garner et. al (US 2021/0359185 A1). Garner discloses (as shown in Fig. 1) a lead tapering, and having a contact surface and a lower surface outside the contact surface, wherein the lower surface extends from a thicker end to a thinner end. ([0027] Each of the vias 106 may be tapered from the second surface 110 to the first surface 108. Therefore, each via 106 has a smaller diameter at the first surface 108 than at the second surface 110.)
Garner teaches that tapering the vias allows for spacing to be reduced. ([0027] The smaller diameter of each via 106 at the first surface 108 allows the spacing between electronic components 104 to be reduced compared to vias that are not tapered. In this way, vias 106 may be precisely placed within a crowded high-resolution display backplane.) Therefore,, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the tapered vias of Garner with Lo in order to reduce spacing.
However, Garner fails to disclose a solder mask disposed on the lower surface and exposing a portion of the lower surface, wherein the solder mask partially covers an encapsulant, wherein the solder mask tapers toward the contact surface.
Other relevant Prior art is Appelt (US 2019/0006308 A1) a solder mask ([0089] The first protection layer 82, such as a solder mask) disposed on the lower surface ([0089] first circuitry 4) and exposing a portion of the lower surface (4), wherein the solder mask (82) partially covers an encapsulant ([0089] encapsulant 3), ([0089] The first protection layer 82, such as a solder mask or other photo-dielectric material, covers the first circuitry 4 and the first surface 31 of the encapsulant 3, and the first protection layer 82 defines one or more openings 821 that expose at least a portion of the first circuitry 4 for external connection.)
However, Appelt fails to disclose wherein the solder mask (82) tapers toward the contact surface.
Regarding Claim 21, Wang further discloses (as shown in Fig. 6) wherein a distribution density of the plurality of first pads (406a) is greater than a distribution density of the plurality of second pads (406b),
wherein a spacing between the plurality of first pads (406a) is less than a spacing between the plurality of second pads (406b),
However, Wang fails to disclose wherein the width of the first pad (406a) is greater than the width of the second pad (406b).
Rather, Wang teaches that the width of the first pad (406a) is less than the width of the second pad (406b). ([0032] he diameters of the bumps formed in the first region 100 are ranging from about 180 µm to 190 µm, preferably about 185 µm; the diameters of the bumps formed in the second region 102 are ranging from about 195 µm to 200 µm, preferably about 197 µm) ([0033] The contact bonding pads and bumps in a region which is closest to the central point are the smallest, while the contact bonding pads and bumps in a region which is farthest to the central point are the largest.) Wang further teaches this is because the stress is greater on the outer portions of the dies. ([0009] With the increasing integration of semiconductor devices, distances between bumps decrease rapidly. Bumps at the edge are liable to peel off because the edges of the chip are far from the central point, and in conditions of periodic variation of temperature, the stress on the bumps at the edge is greater than that closer to the central point. In order to maintain the mechanical intensity of a bump, volume of the bump needs to be enlarged) Therefore, it would not be obvious to make the inner pads wider than the intermediate pads.
Regarding Claim 23, Lin in view of Wang fails to disclose wherein the second solder (408b) extends laterally beyond an inner edge of the carrier (312),
wherein the inner edge faces a terminal of the carrier (312).
Regarding Claim 24, Claim 24 depends from Claim 23 and contains allowable subject matter for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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