Prosecution Insights
Last updated: July 17, 2026
Application No. 18/437,218

MATERIAL STACK WITH IMPROVED DEVICE PERFORMANCE IN PERPENDICULARLY MAGNETIZED HEUSLER FILMS

Non-Final OA §102§103
Filed
Feb 08, 2024
Examiner
JOHNSON, CHRISTOPHER A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
471 granted / 560 resolved
+16.1% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
581
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
81.3%
+41.3% vs TC avg
§102
8.7%
-31.3% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 560 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Election was made without traverse in the reply filed on 5/4/2026. Applicant has elected Group II and Species i, corresponding to claims 1-13 and 15-23. Invention Group I and Species ii, corresponding to claims 14 and 24-25, are withdrawn from further consideration. Information Disclosure Statements The information disclosure statements (IDS) submitted recently have been considered by the examiner. Specification The specification submitted 2/8/2024 has been accepted by the examiner. Drawings The drawings submitted on 2/8/2024 have been accepted by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jeong (US # 20220223783). PNG media_image1.png 387 308 media_image1.png Greyscale Regarding Claim 1, Jeong ‘783 teaches a magnetoresistive random-access memory cell (see Fig. 2B and corresponding text), comprising: a substrate (201); a seed layer (204) outward of the substrate ([0048], 28, 38); a resistive layer (220) outward of the seed layer; an ultra-thin templating layer (210B), outward of the resistive layer, comprising a binary alloy ([0036]) having an alternating layer lattice structure, the ultra-thin templating layer having a thickness of 7-30 Angstroms ([0036]); and a Heusler layer (230) located outward of the ultra-thin templating layer, the Heusler layer comprising a Heusler compound and exhibiting perpendicular magnetic anisotropy (PMA) ([0027, 35, 55]). Regarding Claim 2, Jeong ‘783 teaches the magnetoresistive random-access memory cell of Claim 1, wherein the Heusler layer is located directly on the ultra-thin templating layer and the ultra-thin templating layer is located directly on the resistive layer (shown in Fig. 2B). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US # 20220223783) in view of Filippou (US # 20230413681). Regarding Claim 21, Jeong ‘783 teaches a magnetoresistive random-access memory cells, as explained in the claim 1 rejection. Although Jeong ‘783 discloses much of the claimed invention, it does not explicitly teach the memory array comprising a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs; a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations; a plurality of magnetoresistive random-access memory cells located at each of the plurality of cell locations, each of the magnetoresistive random-access memory cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Filippou ‘681 is in the same or analogous field, and it teaches a memory array (500; Fig. 5 and see corresponding text) comprising a plurality of bit lines (510) and a plurality of complementary bit lines (512) forming a plurality of bit line-complementary bit line pairs; a plurality of word lines (508) intersecting the plurality of bit line pairs at a plurality of cell locations (504); a plurality of magnetoresistive random-access memory cells (502) located at each of the plurality of cell locations, each of the magnetoresistive random-access memory cells being electrically connected to a corresponding bit line (shown) and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines (shown via transistor 506). A person having ordinary skill in the art would have recognized that placing the memory cells of Jeong ‘783 within the architecture suggested by Filippou ‘681 would be obvious. Specifically, the modification suggested by Filippou ‘681 would be to employ a memory array comprising a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs; a plurality of word lines intersecting the plurality of bit line pairs at a plurality of cell locations; a plurality of magnetoresistive random-access memory cells located at each of the plurality of cell locations, each of the magnetoresistive random-access memory cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding one of the complementary bit lines under control of a corresponding one of the word lines. The rationale for this obvious modification is that this circuit array is standard architecture for all STT-MRAM and would function predictably with the cells of Jeong ‘783. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of these architectures are well known in the art (see MPEP 2144.01). Regarding Claim 22, this recitation is rejected for the same essential reasons as claim 2. Allowable Subject Matter Claims 3-13, 15-20, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding Claim 3, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including a nitride layer, outward of the substrate, and having a nitride layer thickness less than 20 Angstroms. Claims 4-13 and 15-20 are dependent upon claim 3. Regarding Claim 23, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including a nitride layer, outward of the substrate, and having a nitride layer thickness less than 20 Angstroms. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Feb 08, 2024
Application Filed
Jun 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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3y 2m to grant Granted Jun 02, 2026
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 560 resolved cases by this examiner. Grant probability derived from career allowance rate.

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