DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 17 recites the limitation “ the redistribution substrate" in lines 5-9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2024/0113032) in view of Lin et al (US Publication No. 2013/0249101).
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Regarding claim 1, Chang discloses a semiconductor package, comprising: a first substrate Fig 5N, 322; a first lower semiconductor chip Fig 5N, 302 disposed on the first substrate Fig 5N, 322; a bridge structure Fig 5N, 320 disposed on the first substrate Fig 5N, 322 and laterally spaced apart from the first lower semiconductor chip Fig 5N; a second substrate Fig 5N, 324 disposed on the first lower semiconductor chip Fig 5N, 302 and the bridge structure Fig 5N, 320; and a first upper semiconductor chip Fig 5N, 352 disposed on the second substrate Fig 5N, 324, wherein the first upper semiconductor chip Fig 5N, 352 is spaced apart from the first lower semiconductor chip Fig 5N, 302, wherein the bridge structure Fig 5N, 320 comprises: a base structure Fig 4A; and conductive vias Fig 4E, 328 disposed in the base structure and contacting the first substrate Fig 5N, 302, and wherein the first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the conductive vias Fig 5N. Chang discloses all the limitations but silent on the arrangement of the bridge structure relative to the upper semiconductor chip.
Whereas Lin discloses wherein the first upper semiconductor chip Fig 11b, 550 is spaced apart from the bridge structure Fig 11b, 140/154/160 in a plan view Fig 11b. Chang and Lin are analogous art because they are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Chang and incorporate the teachings of Lin as an alternative arrangement that improve device performance.
Regarding claim 12, Chang discloses a molding layer Fig 5N, 318 disposed between the first substrate Fig 5N, 322 and the second substrate Fig 5N, 324, wherein the molding layer Fig 5N, 318 covers sidewalls of the base structure, and is spaced apart from the conductive vias Fig 5N.
Claims 2, 7-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2024/0113032) and Lin et al (US Publication No. 2013/0249101) in view of Lee et al (US Publication No. 2022/0310577).
Regarding claim 2, While Lin discloses wherein the first upper semiconductor chip Fig 11b, 550 is spaced apart from the bridge structure Fig 11b, 140/154/160 in a plan view Fig 11b. Chang and Lin discloses all the limitations but silent on the specific arrangement of the lower and upper semiconductor chips relative to the bridge structure. Whereas Lee discloses wherein the bridge structure Fig 4A, 200 is disposed between the first lower semiconductor chip Fig 4A, 700 and the first upper semiconductor chip Fig 4A, 620. Chang and Lee are analogous art because they are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Chang and incorporate the teachings of Lee as an alternative arrangement that improve device performance.
Regarding claim 7, Lee in view of Chang discloses conductive posts Fig 4A, 350PG laterally spaced apart from the first lower semiconductor chip, on an upper surface of the first substrate, wherein the conductive vias Fig 4A, 350s have a first pitch, wherein the conductive posts Fig 4A, 350PG have a second pitch, and wherein the first pitch is less than the second pitch. Fig 4A.
Regarding claim 8, Lee in view of Chang discloses wherein the conductive vias comprise signal vias, and wherein a voltage is configured to supply to the conductive post ¶0073-0074.
Regarding claim 10, Lee in view of Chang discloses a second upper semiconductor chip Fig 4B, 620 disposed on the second substrate Fig 4B, 120, and vertically spaced apart from an upper surface of the first lower semiconductor chip Fig 4B, 620, wherein the first lower semiconductor chip Fig 4B, 700 further comprises through vias penetrating an inside thereof Fig 4B, and wherein the second upper semiconductor chip is electrically connected to the through vias by the second substrate Fig 4B.
Claims 3-6, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2024/0113032) and Lin et al (US Publication No. 2013/0249101)in view of Beyne et al (US Publication No. 2018/0061741).
Regarding claim 3, Chang discloses all the limitations but silent on having a second lower chip. Whereas Beyne discloses a second lower semiconductor chip Fig 2D, 1 disposed on the first substrate Fig 2A-2H and laterally spaced apart from the first lower semiconductor chip Fig 2D, 1, wherein the bridge structure Fig 2D, 16 is disposed between the first lower semiconductor chip and the second lower semiconductor chip Fig 2A-2H. Chang and Beyne are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Chang to incorporate additional devices to improve device performance.
Regarding claim 4, Beyne discloses spacing ¶0038 bust silent on the specific distance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the distance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Regarding claim 5, Beyne discloses wherein one sidewall of the second lower semiconductor (chip faces a first sidewall of the first lower semiconductor chip Fig 2D.
Regarding claim 6, Beyne discloses wherein a length of the one sidewall of the second lower semiconductor chip and a length of the first sidewall of the first lower semiconductor chip are equal to each other or have a difference of about 10 μm or less Fig 2H.
Regarding claim 11, Beyne discloses wherein the first upper semiconductor chip is provided in plural, wherein the bridge structure is provided in plural, and wherein the number of the plurality of first upper semiconductor chips is equal to the number of the plurality of bridge structures Fig 2H.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US Publication No. 2024/0113032) and Lin et al (US Publication No. 2013/0249101) in view of Cheng et al (US Publication No. 2023/0026676).
Regarding claim 9, Chang discloses all the limitation but silent on the type of semiconductor chip. Whereas Cheng discloses wherein the first lower semiconductor chip comprises a first chiplet, and wherein the first upper semiconductor chip comprises a second chiplet Fig 11. Chang and Cheng are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of chip as an alternative device known in the art.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne et al (US Publication No. 2018/0061741) in view of Chang et al (US Publication No. 2024/0113032) ,Cheng et al (US Publication No. 2023/0026676) and Lin et al (US Publication No. 2013/0249101).
Regarding claim 13, Beyne discloses a semiconductor package, comprising: a first substrate Fig 2E, 3; a first lower chip Fig 2E, 1 disposed on the first substrate Fig 2E; a second lower chip Fig 2E, 1 disposed on the first substrate and laterally spaced apart from the first lower chip Fig 2E; a bridge structure Fig 2E, 16 disposed on the first substrate Fig 2E,3, between the first lower chip Fig 2E, 1 and the second lower chip Fig 2E, 1; and a first upper chip Fig 2E, 15 wherein the first upper chip Fig 2E, 15 is electrically connected to the first lower chip Fig 2E, 1 via the bridge structure Fig 2E, 16. Beyne discloses all the limitations but silent on the second substate. Whereas Chang discloses a semiconductor package Fig 5N, comprising: a first substrate Fig 5N, 322; a first lower chip Fig 5N, 302 disposed on the first substrate; a bridge structure Fig 5N, 320 disposed on the first substrate Fig 5N, 322, a second substrate Fig 5N, 324 disposed on the first lower chip Fig 5N, 302 and the bridge structure Fig 5N, 320; and a first upper chip Fig 5N, 352 disposed on the second substrate Fig 5N, 324, wherein the first upper chip Fig 5N, 352 is electrically connected to the first lower chip Fig 5N, 302 via the second substrate Fig 5N, 324 and the bridge structure Fig 5N, 320. Beyne and Chang are analogous art because they are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Beyne because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Beyne and incorporate the teachings of Chang as an alternative arrangement that improve device performance. Beyne discloses all the limitation but silent on the type of semiconductor chip. Whereas Cheng discloses wherein the first lower semiconductor chip comprises a first chiplet, and wherein the first upper semiconductor chip comprises a second chiplet Fig 11. Beyne and Cheng are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Beyne because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of chip as an alternative device known in the art. Beyne discloses all the limitations but silent on the arrangement of the bridge structure relative to the upper semiconductor chip.
Whereas Lin discloses wherein the first upper chiplet Fig 11b, 550 is spaced apart from the bridge structure Fig 11b, 140/154/160 in a plan view Fig 11b. Beyne and Lin are analogous art because they are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Beyne and incorporate the teachings of Lin as an alternative arrangement that improve device performance.
Regarding claim 14, Beyne in view of Cheng discloses wherein the first upper chiplet is spaced apart from the first lower chiplet Fig 2H.
Regarding claim 15, Beyne in view of Cheng discloses wherein the second lower chiplet comprises a first edge chiplet, a second edge chiplet, a third edge chiplet, and a fourth edge chiplet, and wherein one sidewall of the first edge chiplet faces a first sidewall of the first lower chiplet, and is spaced apart from the first sidewall of the first lower chiplet, wherein one sidewall of the second edge chiplet faces a second sidewall of the first lower chiplet, and is spaced apart from the second sidewall of the first lower chiplet, wherein one sidewall of the third edge chiplet faces a third sidewall of the first lower chiplet, and is spaced apart from the third sidewall of the first lower chiplet, and wherein one sidewall of the fourth edge chiplet faces a fourth sidewall of the first lower chiplet, and is spaced apart from the fourth sidewall of the first lower chiplet Fig 2H.
Regarding claim 16, Beyne in view of Cheng discloses wherein the one sidewall of the first edge chiplet extends parallel to the first sidewall of the first lower chiplet, wherein the one sidewall of the second edge chiplet extends parallel to the second sidewall of the first lower chiplet, wherein the one sidewall of the third edge chiplet extends parallel to the third sidewall of the first lower chiplet, and wherein the one sidewall of the fourth edge chiplet extends parallel to the fourth sidewall of the first lower chiplet Fig 2H.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication No. 2022/0310577) in view of Beyne et al (US Publication No. 2018/0061741) and Lin et al (US Publication No. 2013/0249101).
Regarding claim 17, Lee discloses a semiconductor package, comprising: a first redistribution substrate Fig 1B, 110 including a first insulating layer Fig 1B, 111, a first seed pattern Fig 1C, 1131, and a first conductive pattern Fig 1C, 1133W disposed on the first seed pattern Fig 1C, 1131, wherein the first insulating layer Fig 1C, 111 comprises photo sensitive polymer ¶0029; a first lower semiconductor chip Fig 4A, 700 disposed on an upper surface of the first redistribution substrate Fig 4A, 110; bridge structures Fig 4A, 200 respectively disposed on the upper surface of the first redistribution substrate Fig 4A, 110, conductive structures Fig 4A, 350 PG disposed on the upper surface of the first redistribution substrate Fig 4A, 110 and laterally spaced apart from the lower semiconductor chips Fig 4A; a first molding layer Fig 4A, 410 disposed on the upper surface of the first redistribution substrate Fig 4A, 110 and covering the first lower semiconductor chip Fig 4A, 700, and the bridge structures Fig 4A, 200; a second redistribution substrate Fig 4A, 120 disposed on the first molding layer Fig 4A, 410 and the conductive structures Fig 4A, 350PG; first upper semiconductor chips Fig 4A, 620 disposed on the second redistribution substrate Fig 4A, 120; and a second molding layer Fig 4A, 420 disposed on an upper surface of the second redistribution substrate Fig 4A, 120, and covering the first upper semiconductor chips Fig 4A, 620, wherein the second redistribution substrate comprises a second insulating layer Fig 4A, a second seed pattern, and a second conductive pattern disposed on the second seed pattern ¶0044, wherein the second insulating layer comprises a photo sensitive polymer¶0044, wherein the first upper semiconductor chips are apart from the first lower semiconductor chip Fig 4A, wherein each of the bridge structures comprises: a base structure Fig 4A, 210; and wherein the first upper semiconductor chips are electrically connected to the first lower semiconductor chip through the second redistribution substrate and the conductive vias Fig 4A. Lee discloses all the limitations but silent on the additional lower chip. Whereas Beyne discloses a first lower semiconductor chip Fig 2E, 1 disposed on an upper surface of the first redistribution substrate Fig 2E, 3; second lower semiconductor chips Fig 2E, 1 disposed on the upper surface of the first redistribution substrate Fig 2E, 3 and laterally spaced apart from the first lower semiconductor chip Fig 2E; bridge structures Fig 2E, 16 respectively disposed on the upper surface of the first redistribution substrate Fig 2E, 3, between the first lower semiconductor chip and the second lower semiconductor chips Fig 2E; a first molding layer Fig 2E, 2 disposed on the upper surface of the first redistribution substrate Fig 2E, 3 and covering the first lower semiconductor chip Fig 2E, 1, the second lower semiconductor chips Fig 2E, 1. wherein each of the bridge structures comprises: a base structure; and conductive vias disposed in the base structure and in contact with the first redistribution substrate Fig 2E. Lee and Beyne are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Lee to incorporate additional devices to improve device performance.
Lee discloses all the limitations but silent on the arrangement of the bridge structure relative to the upper semiconductor chip.
Whereas Lin discloses wherein the first upper semiconductor chip Fig 11b, 550 is spaced apart from the bridge structure Fig 11b, 140/154/160 in a plan view Fig 11b. Lee and Lin are analogous art because they are directed to semiconductor packages and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Lee and incorporate the teachings of Lin as an alternative arrangement that improve device performance.
Regarding claim 18, Lee in view of Beyne discloses wherein the conductive structures comprise conductive posts, wherein the first upper semiconductor chips are electrically connected to the conductive posts through the second redistribution substrate, wherein the conductive vias have a first pitch, and wherein the conductive posts have a second pitch that is greater than the first pitch Fig 4A.
Regarding claim 19, Beyne discloses spacing ¶0038 bust silent on the specific distance. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the distance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication No. 2022/0310577) in view of Beyne et al (US Publication No. 2018/0061741) and Lin et al (US Publication No. 2013/0249101) and in further view of Pappu et al (US Publication No. 2019/0041959).
Regarding claim 20, Lee discloses all the limitations but silent on the type of chip. Whereas Pappu discloses wherein the semiconductor chip comprises a first communication intellectual property (IP) unit ¶0025. Lee and Pappu are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of chip and incorporate the teachings of Pappu as an alternative chip to improve the package performance as a design choice.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811
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