Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed March 17, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 11, 16
b. Pending: 1-20
Claims 1-20 have been amended.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 04/05/2023 and another application filed in Korea on 06/21/2023. While a certified copy of the KR10-2023-0079448 application was received on February 25, 2026, applicant has not filed a certified copy of the KR10-2023-0044977 application as required by 37 CFR 1.55.
Drawings
The drawings were received on March 17, 2026. These drawings are acceptable.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following explanation is regarding this limitation, emphasis added, presented as included in claims 1 and 11, and in claim 16, respectively:
From claims 1 and 11: “wherein each of the plurality of memory cells outputs a 1-bit output, and wherein memory cells included in a same column output bits corresponding to a same bit position of words stored in different rows of the M x N array.”
From claim 16: “wherein each of the memory cells included in the plurality of multi-bit cells outputs a 1- bit output, and wherein memory cells included in multi-bit cells arranged in a same column of the M x N array output bits corresponding to a same bit position of words stored in different rows of the M x N array.”
The above limitation is indefinite because it is unclear how the bolded section contains any distinguishing features as compared to a typical array of memory cells arranged in M rows with word line connections and N columns with bit line connections. Per MPEP § 2173.02, part “II. THRESHOLD REQUIREMENTS OF CLARITY AND PRECISION,” “If the language of the claim is such that a person of ordinary skill in the art could not interpret the metes and bounds of the claim so as to understand how to avoid infringement, a rejection of the claim under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, is appropriate.”
All dependent claims carry the same deficit and henceforth rejected.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Sever (US Pub. 20140104936 A1). Sever paras. [0027] and [0035]-[0039], and Figs. 1 and 3 are relevant to claims 1, 11, and 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sever (US Pub. 20140104936 A1).
Regarding independent claim 16, Sever discloses a multi-bit cell memory device ([0049]: the memory array could form a configuration memory of a configurable logic device) comprising:
a plurality of multi-bit cells (Fig. 1: memory cells 102; [0036]) arranged in an M x N array having M rows and N columns and including a plurality of memory cells sequentially connected along a row direction of the M x N array, wherein M and N are natural numbers (memory array 100; [0035]); and
a plurality of data lines (complementary write inputs WR0 and WR1; [0038]), where each of the data lines is commonly connected to the plurality of multi-bit cells of a corresponding one of the M rows ([0038]: write signals on the common write lines),
wherein each of the memory cells included in the plurality of multi-bit cells outputs a 1- bit output ([0037]: Each of the memory cells 102 stores one bit of data, and thus the memory array 100 of FIG. 1 stores 8 bits of data. Of course, the memory array could be much larger, for example storing up to 1 k bit of data or more), and wherein memory cells included in multi-bit cells arranged in a same column of the M x N array output bits corresponding to a same bit position of words stored in different rows of the M x N array ([0039]: the data output D.sub.OUT of each memory cell is for example permanently and independently coupled to one or more output ports. In the example of FIG. 1, the data outputs D.sub.OUT of each of the memory cells 102 is connected to an output port 105A and to an output port 105B; [0040]: The multiplexers 106A to 112A respectively provide output signals OUT0 to OUT3 corresponding to the data selected to be read from the memory cells of columns COL0 to COL3 respectively. Examiner asserts that, per Applicant arguments, the invention of Sever “defines a structured architecture in which rows correspond to words and columns correspond to fixed bit positions across those words”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) in view of Maillard et al. (US Pat. 9825632 B1; “Maillard”).
Independent claim 1 contains limitations that are mostly the same as the limitations of claim 16, and those limitation are thus rejected for the same reasons using Sever.
Further through Sever:
a plurality of first clock lines ([0027]: first clock line)
a plurality of second clock lines ([0027]: second clock line)
Sever does not explicitly disclose:
a plurality of first clock lines, where each of the first clock lines is commonly connected to the memory cells of a corresponding one of the N columns;
a plurality of second clock lines, wherein each of the second clock lines is commonly connected to the memory cells of a corresponding one of the N columns; and
However, Maillard teaches:
a plurality of first clock lines (Fig. 3: clock signal line 302; col. 3, lines 48-51), where each of the first clock lines is commonly connected to the memory cells of a corresponding one of the N columns (per Fig. 5, Clk_a is connected to all memory elements of a column, e.g.: 306, 310, 314, 318,…334);
a plurality of second clock lines (Fig. 5: second clock signal line 304; col. 3, lines 48-51), wherein each of the second clock lines is commonly connected to the memory cells of a corresponding one of the N columns (per Fig. 5, Clk_b is connected to all memory elements of a column, e.g.: 306, 310, 314, 318,…334 or 308, 312, 316, 320…); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to Sever wherein there is a plurality of second clock lines, wherein each of the second clock lines is commonly connected to the memory cells of a corresponding one of the N columns in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 2, Sever and Maillard together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells is a latch ([0038]: each of the memory cells 102 is based on a latch; [0068]: Rather than the inverters 202, 204 of memory cell 102, the memory cell 302 for example comprises a pair of cross-coupled inverters 402, 403, which are identical to inverters 202 and 204, except that they each comprise an additional PMOS transistor having its gate coupled to same storage node as the other PMOS and NMOS transistors. Examiner concludes that the memory cells 302 of Fig. 3, like the memory cells 102 of Fig. 1, are latches) or flip-flop.
Regarding claim 3, Sever and Maillard together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells includes a data pin ([0008]: each memory cell further comprises a data output, each of the data outputs being independently connected to an output port of the memory array), and
wherein each of the plurality of data lines is commonly connected to the data pins included in each row of the M rows (output port 105A and output port 105B; [0039]).
Regarding claim 5, Sever and Maillard together disclose the limitations of claim 1, and further through Sever:
wherein a clock signal (Fig. 3: clock signal CKSCAN; [0063]) is applied to the plurality of first clock lines ([0027]: alternate memory cells of the test chain receive a clock signal on a first clock line, and the other memory cells of the test chain receive the inverse of the clock signal on a second clock line), and
wherein an inverted clock signal of the clock signal (inverse clock
C
K
-
SCAN; [0063]) is applied to the plurality of second clock lines ([0027]).
Also, Maillard teaches:
wherein an inverted clock signal of the clock signal (col. 4, lines 53-54: The additional inverters required to generate the extra clock signal; col. 4, lines 58-61: According to the implementation of FIGS. 5 and 6, each memory elements receives both the first clock signal (Clk_a) and the second clock signal (Clk_b). Examiner concludes that Clk_b is an inverted version of Clk_a) is applied to the plurality of second clock lines (Fig. 5: Clk_b).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein an inverted clock signal of the clock signal is applied to the plurality of second clock lines in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 6, Sever and Maillard together disclose the limitations of claim 5, and further through Sever:
configured to apply the inverted clock signal to the plurality of second clock lines ([0063]; [0027])
Sever does not explicitly disclose:
a plurality of clock inverters disposed between an O-th column and a P-th column of the M x N array, and configured to apply the inverted clock signal to the plurality of second clock lines, wherein O and P are natural numbers.
However, Maillard teaches:
a plurality of clock inverters (per Fig. 6, the first local clock generator 208 contains multiple inverters) disposed between an O-th column and a P-th column of the M x N array (Fig. 8 illustrates config/clock distribution regions 809 disposed between vertical columns of logic blocks; col. 6, lines 29-31: The config/clock distribution regions 809 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA; col. 6, lines 39-40: FIG. 8 is intended to illustrate only an exemplary FPGA architecture), and configured to apply the inverted clock signal to the plurality of second clock lines (col. 4, lines 32-39: As is apparent in FIG. 4, the first memory element of the pair of memory elements (i.e. the memory element in the first column) is configured to receive one of the two, separate clock signals generated by the local clock generator 208, and the second memory element of the pair of memory elements (i.e. the memory element in the second column) is configured to receive the other clock signal of the two clock signals), wherein O and P are natural numbers (the columns that config/clock distribution regions 809 are disposed between in Fig. 8 are natural numbers, e.g. the right instance of 809 may be between columns 30 and 31).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein there are a plurality of clock inverters disposed between an O-th column and a P-th column of the M x N array, and configured to apply the inverted clock signal to the plurality of second clock lines, wherein O and P are natural numbers in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 7, Sever and Maillard together disclose the limitations of claim 6. Sever does not disclose:
wherein a first array including a first column to the O-th column of the M x N array and a second array including the P-th column to N-th column of the M x N array have a same array size.
However, Maillard teaches:
wherein a first array including a first column to the O-th column of the M x N array and a second array including the P-th column to N-th column of the M x N array have a same array size (see the annotated image of Fig. 8 below; the two indicated groups of logic blocks may be first and second arrays).
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565
760
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein a first array including a first column to the O-th column of the M x N array and a second array including the P-th column to N-th column of the M x N array have a same array size in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 17, Sever discloses the limitations of claim 16. The limitations of claim 17 are the same as limitations from claim 1, and are thus rejected for the same reasons.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) and Maillard (US Pat. 9825632 B1), and further in view of Roger et al. (WO 9713324 A1; “Roger”).
Regarding claim 4, Sever and Maillard together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells (Fig. 3: 302) includes a clock pin ([0059]: each of the memory cells 302 comprises…a scan clock input), and
Also, Maillard teaches:
a clock pin (col. 5, lines 53-54: specialized input/output blocks (I/O) 807 (e.g., configuration ports and clock ports))
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein there is a clock pin in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Neither Sever nor Maillard disclose:
wherein each of the plurality of first clock lines is commonly connected to the clock pins included in each column of the N columns.
However, Roger teaches:
wherein each of the plurality of first clock lines is commonly connected to the clock pin included in each column of the N columns (page 24, lines 3-15: Each array zone (10 x 10 core cells) has ten port cells on each side (see Figure 2.I.A). The port cells above and below a zone are call the Vertical Port Cells…Port cells also support connections between medium busses in adjacent zones. All 6 medium busses in each row/column connect to the port cells (M1..6). Primary clocks and resets are distributed via the vertical port cells. Examiner concludes that each column may have a port cell that distributes the primary clock signal, meaning each column has a clock pin).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Roger to modified Sever wherein each of the plurality of first clock lines is commonly connected to the clock pin included in each column of the N columns in order to increase circuit and cell density without increasing overall device size (Roger, page 3, lines 17-22).
Claims 8-9 and 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) and Maillard (US Pat. 9825632 B1), and further in view of Kim (US Pub. 20150049550 A1).
Regarding claim 8, Sever and Maillard together disclose the limitations of claim 1. Sever and Maillard disclose an M x N array.
Neither Sever nor Maillard disclose:
a plurality of multiplexers disposed between an O-th column and a P-th column of the M x N array, and configured to output one output data among the output data of each column of the M x N array based on a selection signal, where O and P are natural numbers smaller than N.
However, Kim teaches:
a plurality of multiplexers (Fig. 6: P/SDC 300, P/SDC 302, data path selector 304; [0073]: P/SDC 300 and P/SDC 302 can be implemented as identical bidirectional n to 1 multiplexor/demultiplexor switches, and data path selector 304 can be implemented as is a bidirectional 2 to 1 multiplexor/demultiplexor switch) disposed between an O-th column and a P-th column of the M x N array ([0045]: FIG. 6 is a circuit schematic embodiment of the parallel/serial data converter shown in FIG. 5; Fig. 5: parallel/serial data conversion selector (P/SCS) 216; [0070]: The parallel/serial data conversion selector 216 is placed such that both sets of datelines are the same physical length, and preferably a minimum physical length to minimize loading capacitance), and configured to output one output data among the output data of each column of the M x N array based on a selection signal ([0073]: Data path selector 304 is controlled by a selection control signal HALF_SEL to allow all n bits of L_DATA to pass through in one logic state), where O and P are natural numbers smaller than N.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of multiplexers are disposed between an O-th column and a P-th column of the M x N array, and configured to output one output data among the output data of each column of the M x N array based on a selection signal, where O and P are natural numbers smaller than N in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 9, Sever, Maillard, and Kim together disclose the limitations of claim 8. Sever and Maillard disclose an M x N array.
Neither Sever nor Maillard disclose:
a plurality of selection signal lines arranged along a column direction of the M x N array and configured to commonly apply the selection signal to each of the plurality of multiplexers.
However, Kim teaches:
a plurality of selection signal lines arranged along a column direction of the M x N array ([0108]: In the example of FIG. 15, memory banks 800 and 802 are identical in configuration as memory bank 200 of FIG. 5…Memory bank 800 provides and receives serial data via a serial data signal called BANK1_DATA while memory bank 802 provides and receives serial data via a serial data signal called BANK2_DATA. BANK1_DATA and BANK2_DATA are coupled to serial transfer switch 804, which selectively couples one of the two to GLOB_DATA depending on which memory bank is being accessed for a read or a program operation. Examiner concludes that because the circuits 216 and 804 are arranged along a column direction and the signals BANK1_DATA and BANK2_DATA are shown in a column direction, all selection signal lines associated with circuits 216 and 804 may be arranged along a column direction as well) and configured to commonly apply the selection signal to each of the plurality of multiplexers ([0110]: FIG. 16 is a circuit schematic of serial transfer switch 804 of FIG. 15, according to one embodiment. Serial transfer switch 804 includes a data bank selector 810, and transmission gates 812, 814 and 816…data bank selector 810 can be implemented with a multiplexor/demultiplexor circuit; [0110]: Data bank selector 810 is controlled by selection signal BANK_SEL, to couple either BANK1_DATA or BANK2_DATA to GLOB_DATA).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of selection signal lines is arranged along a column direction of the M x N array and configured to commonly apply the selection signal to each of the plurality of multiplexers in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Independent claim 11 contains a second limitation that is mostly the same as the limitations of claims 8 and 9, and that limitation is thus rejected for the same reasons using Sever, Maillard, and Kim. Independent claim 11 also contains a last limitation that is exactly the same as the last limitation of claim 1, and that limitation is thus rejected for the same reasons using Sever and Maillard.
Further through Sever:
a plurality of memory cells (Fig. 3: 302) arranged in an M x N array having M rows and N columns ([0035]), wherein each of the memory cells of a corresponding one of the M rows is configured to commonly receive input data (scan input data signal SCAN_IN; [0062]), and each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal (CKSCAN) and an inverted clock signal (
C
K
-
SCAN); and
wherein M and N are natural numbers (per Fig. 3, M is 4 and N is 4),
Also, Maillard teaches:
and each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal and an inverted clock signal (col. 3, lines 20-28: Each column of memory elements comprises a clock generator coupled to receive the clock signal and generate a corresponding plurality of clock signals (shown here as a first clock signal (Clk_a) and a second clock signal (Clk_b)) that are coupled to the memory elements. More particularly, a first local clock generator 208 is coupled to receive the CLK signal and generate the first and second clock signals that are coupled to the memory element 210; col. 4, lines 58-61); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal and an inverted clock signal in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 12, Sever, Maillard, and Kim together disclose the limitations of claim 11. The limitations of claim 12 are the same as limitations from claim 8, and are thus rejected for the same reasons.
Regarding claim 14, Sever, Maillard, and Kim together disclose the limitations of claim 11. Claim 14 recites the exact same limitations as claim 2, and is henceforth rejected for the same reasons.
Regarding claim 15, Sever, Maillard, and Kim together disclose the limitations of claim 11. The limitations of claim 15 are the same as limitations from claim 6, and are thus rejected for the same reasons.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1), Maillard (US Pat. 9825632 B1), and Kim (US Pub. 20150049550 A1), and further in view of Best et al. (US Pub. 20220139446 A1; “Best”).
Regarding claim 10, Sever, Maillard, and Kim together disclose the limitations of claim 8. Kim discloses:
outputting the one output data ([0073])
Neither Sever, Maillard, nor Kim disclose:
a plurality of output pins connected to the plurality of multiplexers,
However, Best teaches:
a plurality of output pins connected to the plurality of multiplexers ([0048]: when a column-latch signal (ColLat) is asserted, the sense amplifier circuit 207…is coupled via array bit lines 208 to a column decoder 210 (or column multiplexer) circuit disposed centrally within the storage array 187, and a column address value, CAdr[11:0], is applied to couple a selected one of 4096 columns of array bit lines 208 to a data I/O circuit 212, thereby…enabling read data to be output from the column of sense amplifiers to the data I/O circuit 212 and thus output to the interface die),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Best to modified Sever wherein a plurality of output pins is connected to the plurality of multiplexers in order to improve power efficiency by separating the storage circuitry from the high-speed logic circuitry (Best, [0037]).
Regarding claim 13, Sever, Maillard, and Kim together disclose the limitations of claim 12. Neither Sever, Maillard, nor Kim disclose:
wherein the plurality of multiplexers are arranged along a column direction of the M x N array.
However, Best teaches:
wherein the plurality of multiplexers are arranged along a column direction of the M x N array ([0048]; Fig. 5B shows the column multiplexer 210 arranged between storage banks. Examiner asserts that a 90-degree rotation of Fig. 5B will result in 210 being arranged in a column direction).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Best to modified Sever wherein the plurality of multiplexers are arranged along a column direction of the M x N array in order to improve power efficiency by separating the storage circuitry from the high-speed logic circuitry (Best, [0037]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) in view of Kim (US Pub. 20150049550 A1).
Regarding claim 18, Sever discloses the limitations of claim 16. Sever discloses a plurality of multi-bit cells, but does not disclose:
a plurality of buffers disposed between any two multi-bit cells among the plurality of multi-bit cells.
However, Kim teaches:
a plurality of buffers (Fig. 5: page buffers 212 and 214; [0069]) disposed between any two multi-bit cells among the plurality of multi-bit cells ([0069]: sectors 202 and 206 have their bitlines coupled to shared page buffer 212, while sectors 204 and 208 have their bitlines coupled to shared page buffer 214; [0068]: FIG. 5 is a block diagram illustrating an example embodiment of the memory bank 104 of FIG. 4A…Memory bank 200 is divided into four memory portions, shown as sectors (sector 1, sector 2, sector 3 and sector 4) 202, 204, 206 and 208. In the physical orientation of the memory bank 200 of FIG. 5, each sector includes bitlines extending in the vertical direction and wordlines extending in the horizontal direction. Examiner concludes that since all of the sectors contain memory cells, the buffers are each disposed between multiple pairs of cells).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of buffers is disposed between any two multi-bit cells among the plurality of multi-bit cells in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 19, Sever and Kim together disclose the limitations of claim 18. Sever discloses a plurality of multi-bit cells, but does not disclose:
wherein the plurality of buffers buffer output data output from one of the two multi-bit cells to generate buffered data and applies the buffered data as input data to the remaining one.
However, Kim teaches:
wherein the plurality of buffers buffer output data output from one of the two multi-bit cells to generate buffered data and applies the buffered data as input data to the remaining one ([0109]: The operation of serial transfer switch 804 described above is called a normal mode of operation. In a direct transfer mode of operation, BANK1_DATA and BANK2_DATA are directly coupled to each other. Accordingly, in the direct transfer mode of operation, the page buffers of memory bank 800 and 802 will be synchronized such that data provided from the page buffers of one memory bank are latched in the page buffers of the other memory bank. Examiner asserts that an exchange of data between memory banks indicates that there is an exchange of data between cells).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein the plurality of buffers buffer output data output from one of the two multi-bit cells to generate buffered data and applies the buffered data as input data to the remaining one in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 20, Sever and Kim together disclose the limitations of claim 18. Sever discloses a plurality of multi-bit cells, but does not disclose:
wherein the any two multi-bit cells are configured to be inverted with each other based on the row direction of the plurality of multi-bit cells.
However, Kim teaches:
wherein the any two multi-bit cells are configured to be inverted with each other based on the row direction of the plurality of multi-bit cells ([0069]: In the presently described configuration of FIG. 5 where wordlines in both halves of the memory bank are logically the same, page buffer 212 senses and latches a first half page of data and page buffer 214 senses and latches a second half page of data; [0072]: The embodiment of FIG. 5 shows a memory bank 200 having left and right halves. In an alternate configuration, the memory array includes only two sectors, such as sectors 202 and 206; Fig. 7B shows a vertically and horizontally symmetrical structure. Examiner concludes that two cells may be “inverted with each other” in the row direction).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein the any two multi-bit cells are configured to be inverted with each other based on the row direction of the plurality of multi-bit cells in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
4/2/2026
Prosecution Insights