Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 7, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 11, 16
b. Pending: 1-20
Claims 1, 3-4, 8, 11, 16, and 20 have been amended.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 7, 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The previous rejections of claims 1-20 under 35 U.S.C. 112(b) have been withdrawn pursuant to claim amendments.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1, 11 and 16:
The second to last limitation of claims 1 and 11 and the last limitation of claim 16 are indefinite because it is not clear how the limitation specifies a unique feature of the invention. Unless the rows and columns of the M x N array are connected in an abnormal fashion, a person possessing ordinary skill in the art would know that the “bit order” within one column is the same as the “bit order” in a different column.
Regarding claim 3, the limitation “wherein each of the plurality of data lines is commonly connected to the cell data pins included in each row of the M rows” is indefinite because a broad interpretation of the limitation is that each data line is connected to each cell via the cell data pins. Examiner suggests amending the language to: “wherein for each row of the M rows, the data line is connected to each cell data pin of the row.”
Regarding claim 4, the limitation “wherein each of the plurality of first clock lines is commonly connected to the cell clock pins included in each column of the N columns” is indefinite because a broad interpretation of the limitation is that each clock line is connected to each cell via the cell clock pins. Examiner suggests amending the language to: “wherein for each column of the N columns, the clock line is connected to each cell clock pin of the column.”
Claim 8 is indefinite because a broad interpretation of the limitation is that the plurality of multiplexers together output one output data. Examiner suggests amending the language as follows: “a plurality of multiplexers disposed between an O-th column and a P-th column of the M x N array, [[and]]each multiplexer configured to output one output data among the 1-bit outputs of the memory cells included in [[each]]the corresponding column of the M x N array based on a selection signal, where O and P are natural numbers smaller than N.”
Regarding claim 20, the phrase “opposite to each other” is indefinite because it is not clear what it means for the two multi-bit cells to be opposite to each other. Claim 18 makes it clear that there is a plurality of buffers in between the two multi-bit cells, so in that regard, it is obvious that the two multi-bit cells are positioned opposite to each other with the buffers in between them. Is there some important symmetry across the axis running vertically through the buffers?
Dependent claims 2-10,12-15 and 17-20 are thus rejected under 35 U.S.C. 112(b) due to the above rejections of independent claims 1, 11, and 16.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Hung et al. (20230317122 A1; “Hung”), Liang et al. (US Pub. 20220128669 A1; “Liang”), and Tu (US Pub. 20180366183 A1). Hung para. [0035] and Fig. 1 is relevant to claims 1, 11, and 16. Liang paras. [0029]-[0030] and Figs. 1 and 5 are relevant to claims 1, 11, and 16. Tu para. [0030] and Fig. 4 is relevant to claims 1, 11, and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) in view of Maillard et al. (US Pat. 9825632 B1; “Maillard”), Hung (20230317122 A1), and Liang (US Pub. 20220128669 A1).
Regarding independent claim 1, Sever discloses a multi-bit memory device ([0049]: the memory array could form a configuration memory of a configurable logic device) comprising:
a plurality of memory cells (Fig. 1: memory cells 102; [0036]) arranged in an M x N array having M rows and N columns, wherein M and N are natural numbers (memory array 100; [0035]);
a plurality of data lines (complementary write inputs WR0 and WR1; [0038]), where each of the data lines is commonly connected to the memory cells of a corresponding one of the M rows ([0038]: write signals on the common write lines),
a plurality of first clock lines ([0027]: first clock line)
a plurality of second clock lines ([0027]: second clock line)
wherein the M rows ([0036]: two rows ROW0 and ROW1) respectively store M words ([0037]: the memory array 100 of FIG. 1 stores 8 bits of data. Examiner concludes that each row stores a 4-bit word), each of the M words includes N bits, and each of the plurality of memory cells outputs a 1-bit output ([0037]: Each of the memory cells 102 stores one bit of data) corresponding to one of the N bits of a word stored in a row in which the memory cell is included ([0037]),
wherein memory cells included in a same column output bits having a same bit order in the M words stored in different rows of the M x N array (Fig. 1 shows a 2 x 4 array), and
Sever does not disclose:
where each of the first clock lines is commonly connected to the memory cells of a corresponding one of the N columns;
where each of the second clock lines is commonly connected to the memory cells of a corresponding one of the N columns; and
device includes M data pins respectively connected to the plurality of data lines and N clock pins respectively connected to the plurality of first clock lines.
However, Maillard teaches:
where each of the first clock lines (Fig. 3: clock signal line 302; col. 3, lines 48-51) is commonly connected to the memory cells of a corresponding one of the N columns (per Fig. 5, Clk_a is connected to all memory elements of a column, e.g.: 306, 310, 314, 318,…334);
wherein each of the second clock lines (Fig. 5: second clock signal line 304; col. 3, lines 48-51) is commonly connected to the memory cells of a corresponding one of the N columns (per Fig. 5, Clk_b is connected to all memory elements of a column, e.g.: 306, 310, 314, 318,…334 or 308, 312, 316, 320…); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to Sever wherein each of the each of the first clock lines is commonly connected to the memory cells of a corresponding one of the N columns, and wherein each of the second clock lines is commonly connected to the memory cells of a corresponding one of the N columns in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Also, through Hung:
device includes M data pins respectively connected to the plurality of data lines ([0035]: One pin can be connected to an input data line carrying serial input data/address signal SI, usable for commands as well. Another pin, or multiple other pins, can be connected to an output data line or output data lines carrying a serial output data signal SO) and N clock pins respectively connected to the first clock lines ([0035]: Another pin can be connected to a clock line carrying serial clock signal SCLK. Hung shows that a clock line may have a pin).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hung to modified Sever wherein the device includes M data pins respectively connected to the plurality of data lines and N clock pins respectively connected to the first clock lines in order to reduce power consumption and improve the speed of operations for CIM devices (Hung, [0046]).
Also, through Liang:
plurality of first clock lines (Fig. 1: sixth clock signal clk6; [0030]: the plurality of sixth clock signals clk6 to the plurality of pixel columns. Examiner notes that there are ‘N’ sixth clock signals because each column of the pixel array has a corresponding sixth clock signal clk6)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Liang to modified Sever wherein the device includes a plurality of first clock lines in order to control phase differences between circuit components including between an array and an output (Liang, [0006]).
Regarding claim 2, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells is a latch ([0038]: each of the memory cells 102 is based on a latch; [0068]: Rather than the inverters 202, 204 of memory cell 102, the memory cell 302 for example comprises a pair of cross-coupled inverters 402, 403, which are identical to inverters 202 and 204, except that they each comprise an additional PMOS transistor having its gate coupled to same storage node as the other PMOS and NMOS transistors. Examiner concludes that the memory cells 302 of Fig. 3, like the memory cells 102 of Fig. 1, are latches) or flip-flop.
Regarding claim 5, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 1, and further through Sever:
wherein a clock signal (Fig. 3: clock signal CKSCAN; [0063]) is applied to the plurality of first clock lines ([0027]: alternate memory cells of the test chain receive a clock signal on a first clock line, and the other memory cells of the test chain receive the inverse of the clock signal on a second clock line), and
wherein an inverted clock signal of the clock signal (inverse clock
C
K
-
SCAN; [0063]) is applied to the plurality of second clock lines ([0027]).
Also, Maillard teaches:
wherein an inverted clock signal of the clock signal (col. 4, lines 53-54: The additional inverters required to generate the extra clock signal; col. 4, lines 58-61: According to the implementation of FIGS. 5 and 6, each memory elements receives both the first clock signal (Clk_a) and the second clock signal (Clk_b). Examiner concludes that Clk_b is an inverted version of Clk_a) is applied to the plurality of second clock lines (Fig. 5: Clk_b).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein an inverted clock signal of the clock signal is applied to the plurality of second clock lines in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 6, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 5, and further through Sever:
configured to apply the inverted clock signal to the plurality of second clock lines ([0063]; [0027])
Sever does not explicitly disclose:
a plurality of clock inverters disposed between an O-th column and a P-th column of the M x N array, and configured to apply the inverted clock signal to the plurality of second clock lines, wherein O and P are natural numbers.
However, Maillard teaches:
a plurality of clock inverters (per Fig. 6, the first local clock generator 208 contains multiple inverters) disposed between an O-th column and a P-th column of the M x N array (Fig. 8 illustrates config/clock distribution regions 809 disposed between vertical columns of logic blocks; col. 6, lines 29-31: The config/clock distribution regions 809 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA; col. 6, lines 39-40: FIG. 8 is intended to illustrate only an exemplary FPGA architecture), and configured to apply the inverted clock signal to the plurality of second clock lines (col. 4, lines 32-39: As is apparent in FIG. 4, the first memory element of the pair of memory elements (i.e. the memory element in the first column) is configured to receive one of the two, separate clock signals generated by the local clock generator 208, and the second memory element of the pair of memory elements (i.e. the memory element in the second column) is configured to receive the other clock signal of the two clock signals), wherein O and P are natural numbers (the columns that config/clock distribution regions 809 are disposed between in Fig. 8 are natural numbers, e.g. the right instance of 809 may be between columns 30 and 31).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein there are a plurality of clock inverters disposed between an O-th column and a P-th column of the M x N array, and configured to apply the inverted clock signal to the plurality of second clock lines, wherein O and P are natural numbers in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 7, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 6. Further, through Maillard:
wherein a first array including a first column to the O-th column of the M x N array and a second array including the P-th column to N-th column of the M x N array have a same array size (see the annotated image of Fig. 8 below; the two indicated groups of logic blocks may be first and second arrays).
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565
760
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Greyscale
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein a first array including a first column to the O-th column of the M x N array and a second array including the P-th column to N-th column of the M x N array have a same array size in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Independent claim 16 contains limitations that are mostly the same as the limitations of claim 1, and those limitation are thus rejected for the same reasons.
Further, through Hung:
multi-bit cells ([0041]: storage elements supporting page read and page write of multiple bits per memory cell)
wherein each of the plurality of multi-bit cells is configured to store more than one bit of data ([0041]),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hung to modified Sever wherein the device includes multi-bit cells wherein each of the plurality of multi-bit cells is configured to store more than one bit of data in order to reduce power consumption and improve the speed of operations for CIM devices (Hung, [0046]).
Regarding claim 17, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 16. The limitations of claim 17 are the same as limitations from claim 1, and are thus rejected for the same reasons.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1), Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), and Liang (US Pub. 20220128669 A1), and further in view of Tu (US Pub. 20180366183 A1).
Regarding claim 3, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells includes a cell data pin ([0008]: each memory cell further comprises a data output, each of the data outputs being independently connected to an output port of the memory array), and
wherein each of the plurality of data lines (Fig. 1: complementary write inputs WR0 and WR1; [0038]) is commonly connected to each row of the M rows ([0038]: write signals on the common write lines).
Neither Sever, Maillard, Hung, nor Liang discloses:
the cell data pins
However, Tu teaches:
the cell data pins ([0030]: As shown in FIG. 4, the data pin of each D flip-flop D2 may be coupled to a fuse F1 to receive the data generated by the fuse F1, and the clock pin of each D flip-flop D2 may be coupled to the clock generator 130 to receive the clock signal; [0002]: memory device technology for transmitting the signals of a fuse array through D flip-flops. Examiner asserts that Tu teaches that D flip-flops each have cell data pins and cell clock pins, and that D flip-flops may be used in memory storage devices. Also see Figs. 1, 2, 6, and 7 of the present application for memory devices that include D flip-flops)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tu to modified Sever wherein the memory device contains cell data pins in order to provide a memory device that includes multiple D flip-flops (Tu, [0007]).
Regarding claim 4, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 1, and further through Sever:
wherein each of the plurality of memory cells (Fig. 3: 302) includes a cell clock pin ([0059]: each of the memory cells 302 comprises…a scan clock input), and
Also, through Maillard:
wherein each of the plurality of first clock lines (Fig. 3: clock signal line 302; col. 3, lines 48-51) is commonly connected to each column of the N columns (per Fig. 5, Clk_a is connected to all memory elements of a column, e.g.: 306, 310, 314, 318,…334).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to modified Sever wherein each of the plurality of first clock lines is commonly connected to each column of the N columns in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Neither Sever, Maillard, Hung, nor Liang discloses:
the cell clock pins
However, Tu teaches:
the cell clock pins ([0030]; see rejection of claim 3 above)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tu to modified Sever wherein the memory device contains cell clock pins in order to provide a memory device that includes multiple D flip-flops (Tu, [0007]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1), Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), and Liang (US Pub. 20220128669 A1) as applied to claim 1 above, and further in view of Kim (US Pub. 20150049550 A1).
Regarding claim 8, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 1. Sever and Maillard disclose an M x N array, and Sever discloses 1-bit outputs of the memory cells.
Neither Sever, Maillard, Hung, nor Liang discloses:
a plurality of multiplexers disposed between an O-th column and a P-th column of the M x N array, and configured to output one output data included in each column of the M x N array based on a selection signal, where O and P are natural numbers smaller than N.
However, Kim teaches:
a plurality of multiplexers (Fig. 6: P/SDC 300, P/SDC 302, data path selector 304; [0073]: P/SDC 300 and P/SDC 302 can be implemented as identical bidirectional n to 1 multiplexor/demultiplexor switches, and data path selector 304 can be implemented as is a bidirectional 2 to 1 multiplexor/demultiplexor switch) disposed between an O-th column and a P-th column of the M x N array ([0045]: FIG. 6 is a circuit schematic embodiment of the parallel/serial data converter shown in FIG. 5; Fig. 5: parallel/serial data conversion selector (P/SCS) 216; [0070]: The parallel/serial data conversion selector 216 is placed such that both sets of datelines are the same physical length, and preferably a minimum physical length to minimize loading capacitance), and configured to output one output data included in each column of the M x N array based on a selection signal ([0073]: Data path selector 304 is controlled by a selection control signal HALF_SEL to allow all n bits of L_DATA to pass through in one logic state), where O and P are natural numbers smaller than N.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of multiplexers are disposed between an O-th column and a P-th column of the M x N array, and configured to output one output data included in each column of the M x N array based on a selection signal, where O and P are natural numbers smaller than N in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 9, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 8. Sever and Maillard disclose an M x N array.
Neither Sever nor Maillard disclose:
a plurality of selection signal lines arranged along a column direction of the M x N array and configured to commonly apply the selection signal to each of the plurality of multiplexers.
However, Kim teaches:
a plurality of selection signal lines arranged along a column direction of the M x N array ([0108]: In the example of FIG. 15, memory banks 800 and 802 are identical in configuration as memory bank 200 of FIG. 5…Memory bank 800 provides and receives serial data via a serial data signal called BANK1_DATA while memory bank 802 provides and receives serial data via a serial data signal called BANK2_DATA. BANK1_DATA and BANK2_DATA are coupled to serial transfer switch 804, which selectively couples one of the two to GLOB_DATA depending on which memory bank is being accessed for a read or a program operation. Examiner concludes that because the circuits 216 and 804 are arranged along a column direction and the signals BANK1_DATA and BANK2_DATA are shown in a column direction, all selection signal lines associated with circuits 216 and 804 may be arranged along a column direction as well) and configured to commonly apply the selection signal to each of the plurality of multiplexers ([0110]: FIG. 16 is a circuit schematic of serial transfer switch 804 of FIG. 15, according to one embodiment. Serial transfer switch 804 includes a data bank selector 810, and transmission gates 812, 814 and 816…data bank selector 810 can be implemented with a multiplexor/demultiplexor circuit; [0110]: Data bank selector 810 is controlled by selection signal BANK_SEL, to couple either BANK1_DATA or BANK2_DATA to GLOB_DATA).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of selection signal lines is arranged along a column direction of the M x N array and configured to commonly apply the selection signal to each of the plurality of multiplexers in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1), Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), Liang (US Pub. 20220128669 A1), and Kim (US Pub. 20150049550 A1) as applied to claim 8 above, and further in view of Best et al. (US Pub. 20220139446 A1; “Best”).
Regarding claim 10, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 8. Kim discloses outputting the one output data. Neither Sever, Maillard, Hung, Liang, nor Kim discloses:
a plurality of output pins connected to the plurality of multiplexers,
However, Best teaches:
a plurality of output pins connected to the plurality of multiplexers ([0048]: when a column-latch signal (ColLat) is asserted, the sense amplifier circuit 207…is coupled via array bit lines 208 to a column decoder 210 (or column multiplexer) circuit disposed centrally within the storage array 187, and a column address value, CAdr[11:0], is applied to couple a selected one of 4096 columns of array bit lines 208 to a data I/O circuit 212, thereby…enabling read data to be output from the column of sense amplifiers to the data I/O circuit 212 and thus output to the interface die),
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Best to modified Sever wherein a plurality of output pins is connected to the plurality of multiplexers in order to improve power efficiency by separating the storage circuitry from the high-speed logic circuitry (Best, [0037]).
Claims 11-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) in view Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), Liang (US Pub. 20220128669 A1), and Kim (US Pub. 20150049550 A1).
Independent claim 11 contains a second limitation that is mostly the same as the limitations of claims 8 and 9, and that limitation is thus rejected for the same reasons. The last three limitations of claim 11 are mostly the same as the last three limitations of claim 1, and those limitations are thus rejected for the same reasons.
Further through Sever:
a plurality of memory cells (Fig. 3: 302) arranged in an M x N array having M rows and N columns ([0035]), wherein each of the memory cells of a corresponding one of the M rows is configured to commonly receive input data (scan input data signal SCAN_IN; [0062]), and each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal (CKSCAN) and an inverted clock signal (
C
K
-
SCAN); and
wherein M and N are natural numbers (per Fig. 3, M is 4 and N is 4),
Also, Maillard teaches:
and each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal and an inverted clock signal (col. 3, lines 20-28: Each column of memory elements comprises a clock generator coupled to receive the clock signal and generate a corresponding plurality of clock signals (shown here as a first clock signal (Clk_a) and a second clock signal (Clk_b)) that are coupled to the memory elements. More particularly, a first local clock generator 208 is coupled to receive the CLK signal and generate the first and second clock signals that are coupled to the memory element 210; col. 4, lines 58-61); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Maillard to Sever wherein each of the memory cells of a corresponding one of the N columns is configured to commonly receive a clock signal and an inverted clock signal in order to reduce the probability of multiple errors induced by an ion strike (Maillard, col. 2, lines 51-54).
Regarding claim 12, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 11. The limitations of claim 12 are the same as limitations from claim 8, and are thus rejected for the same reasons.
Regarding claim 14, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 11. Claim 14 recites the exact same limitations as claim 2, and is henceforth rejected for the same reasons.
Regarding claim 15, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 11. The limitations of claim 15 are the same as limitations from claim 6, and are thus rejected for the same reasons.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1) in view Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), Liang (US Pub. 20220128669 A1), and Kim (US Pub. 20150049550 A1) as applied to claim 12 above, and further in view of Best (US Pub. 20220139446 A1).
Regarding claim 13, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 12. Neither Sever, Maillard, nor Kim disclose:
wherein the plurality of multiplexers are arranged along a column direction of the M x N array.
However, Best teaches:
wherein the plurality of multiplexers are arranged along a column direction of the M x N array ([0048]; Fig. 5B shows the column multiplexer 210 arranged between storage banks. Examiner asserts that a 90-degree rotation of Fig. 5B will result in 210 being arranged in a column direction).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Best to modified Sever wherein the plurality of multiplexers are arranged along a column direction of the M x N array in order to improve power efficiency by separating the storage circuitry from the high-speed logic circuitry (Best, [0037]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sever (US Pub. 20140104936 A1), Maillard (US Pat. 9825632 B1), Hung (20230317122 A1), and Liang (US Pub. 20220128669 A1) as applied to claim 16 above, and further in view of Kim (US Pub. 20150049550 A1).
Regarding claim 18, Sever, Maillard, Hung, and Liang together disclose the limitations of claim 16. Sever discloses a plurality of multi-bit cells. Neither Sever, Maillard, Hung, nor Liang discloses:
a plurality of buffers disposed between any two multi-bit cells among the plurality of multi-bit cells.
However, Kim teaches:
a plurality of buffers (Fig. 5: page buffers 212 and 214; [0069]) disposed between any two multi-bit cells among the plurality of multi-bit cells ([0069]: sectors 202 and 206 have their bitlines coupled to shared page buffer 212, while sectors 204 and 208 have their bitlines coupled to shared page buffer 214; [0068]: FIG. 5 is a block diagram illustrating an example embodiment of the memory bank 104 of FIG. 4A…Memory bank 200 is divided into four memory portions, shown as sectors (sector 1, sector 2, sector 3 and sector 4) 202, 204, 206 and 208. In the physical orientation of the memory bank 200 of FIG. 5, each sector includes bitlines extending in the vertical direction and wordlines extending in the horizontal direction. Examiner concludes that since all of the sectors contain memory cells, the buffers are each disposed between multiple pairs of cells).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein a plurality of buffers is disposed between any two multi-bit cells among the plurality of multi-bit cells in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 19, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 18. Sever discloses a plurality of multi-bit cells.
Also, Kim teaches:
wherein the plurality of buffers buffer output data output from one of the two multi-bit cells to generate buffered data and applies the buffered data as input data to the remaining one ([0109]: The operation of serial transfer switch 804 described above is called a normal mode of operation. In a direct transfer mode of operation, BANK1_DATA and BANK2_DATA are directly coupled to each other. Accordingly, in the direct transfer mode of operation, the page buffers of memory bank 800 and 802 will be synchronized such that data provided from the page buffers of one memory bank are latched in the page buffers of the other memory bank. Examiner asserts that an exchange of data between memory banks indicates that there is an exchange of data between cells).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein the plurality of buffers buffer output data output from one of the two multi-bit cells to generate buffered data and applies the buffered data as input data to the remaining one in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Regarding claim 20, Sever, Maillard, Hung, Liang, and Kim together disclose the limitations of claim 18. Sever discloses a plurality of multi-bit cells.
Also, Kim teaches:
wherein the any two multi-bit cells are configured to be opposite to each other based on the row direction of the plurality of multi-bit cells ([0069]: In the presently described configuration of FIG. 5 where wordlines in both halves of the memory bank are logically the same, page buffer 212 senses and latches a first half page of data and page buffer 214 senses and latches a second half page of data; [0072]: The embodiment of FIG. 5 shows a memory bank 200 having left and right halves. In an alternate configuration, the memory array includes only two sectors, such as sectors 202 and 206; Fig. 7B shows a vertically and horizontally symmetrical structure. Examiner concludes that two cells may be “opposite to each other” in the row direction).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified Sever wherein the any two multi-bit cells are configured to be opposite to each other based on the row direction of the plurality of multi-bit cells in order to implement a memory system with multiple memory banks while minimizing an increase in chip area (Kim, [0058]).
Conclusion
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
9/15/2026
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