Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I sub (a) (Claims 1-20) in the reply filed on 08/17/2026 is acknowledged.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/09/2024 and 07/08/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 10, 12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (US 2019/0393214).
As for claim 1, Lilak et al. disclose Figs. 1-2B and the related text a stacked integrated circuit device, comprising:
a lower active region 211;
a lower gate pattern 213 surrounding the lower active region;
a lower dielectric layer 215 between the lower active region and the lower gate pattern (Fig. 2);
an intermediate insulating layer 257/255 on the lower active region (Fig. 2);
an upper active region 231 on the intermediate insulating layer (Fig. 2);
an upper gate pattern 233 surrounding the upper active region and covering the lower gate pattern (Fig. 2); and
an upper dielectric layer 235 between the upper active region and the upper gate pattern (Fig. 2) wherein an upper surface of the lower gate pattern 213 is located lower in a vertical direction than an upper surface of the intermediate insulating layer 257/255 (Fig. 2), and the lower gate pattern 213 surrounds at least a portion of a side surface of the intermediate insulating layer 275/255 (Fig. 2).
As for claim 2, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, wherein a work function of the upper gate pattern 233 and a work function of the lower gate pattern 213 are different from each other ([0032]-[0033]).
As for claim 6, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, further comprising a gate insulating layer 215 between the lower gate pattern 213 and the upper gate pattern 233 (Fig. 2).
As for claim 10, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, wherein the lower gate pattern 213 has an upper surface perpendicular to the vertical direction (Fig. 2).
As for claim 12, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, wherein a lowest point of an upper surface of the lower gate pattern 213 is located higher in the vertical direction than an upper surface of the lower active region (Fig. 2).
As for claim 14, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, wherein: a portion of the intermediate insulating layer 257/255 is in contact with the lower gate pattern, and a remaining portion of the intermediate insulating layer is in contact with the upper gate pattern (Fig. 2).
As for claim 15, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 14, wherein: a portion of a (upper/lower) side surface of the intermediate insulating layer 257/255 is covered by the upper dielectric layer 235, and a remaining portion of the side surface of the intermediate insulating layer 257/255 is covered by the lower dielectric layer 215 (fig. 2).
Claims 1, 3-4, 7 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2020/0294866).
As for claim 1, Cheng et al. disclose in Figs. 1A-10B and the related text a stacked integrated circuit device, comprising:
a lower active region 110;
a lower gate pattern 804 surrounding the lower active region (Figs. 10A-10B);
a lower dielectric layer 802 between the lower active region and the lower gate pattern (Figs. 10A-10B);
an intermediate insulating layer 312 on the lower active region (Figs. 10A-10B);
an upper active region 110 on the intermediate insulating layer (Figs. 10A-10B);
an upper gate pattern 804 surrounding the upper active region and covering the lower gate pattern (Figs. 10A-10B); and
an upper dielectric layer 802 between the upper active region and the upper gate pattern (Figs. 10A-10B), wherein an upper surface of the lower gate pattern 804 is located lower in a vertical direction than an upper surface of the intermediate insulating layer (Figs. 10A-10B), and the lower gate pattern 804 surrounds at least a portion of a (upper) side surface of the intermediate insulating layer 312 (Figs. 10A-10B).
As for claim 3, Cheng et al. disclose the stacked integrated circuit device as claimed in claim 1, further comprising: a pair of lower source/drain regions 502 on both sides of the lower gate pattern (Fig. 10A-10B); and a pair of upper source/drain regions 604 on both sides of the upper gate pattern (Fig. 10A-10B), wherein the lower active region (lower 110) includes surfaces in contact with the pair of lower source/drain regions, and the upper active region (upper 110) includes surfaces in contact with the pair of upper source/drain regions (Fig. 10A-10B).
As for claim 4, Cheng et al. disclose the stacked integrated circuit device as claimed in claim 3, wherein a type of a dopant with which the pair of upper source/drain regions 106 are doped and a type of a dopant with which the pair of lower source/drain regions 104 are doped are different from each other [0051].
As for claim 7, Cheng et al. disclose the stacked integrated circuit device as claimed in claim 6, wherein the gate insulating layer 802 is conformally formed on a surface of the lower gate pattern 804 (Fig. 10A-10B).
As for claim 16, Cheng et al. disclose in Figs. 1A-10B and the related text a stacked integrated circuit device, comprising:
a lower active region 110 including a first lower active region (lower 110 of 504) and a second lower active region (upper 110 of 504) spaced apart in a horizontal direction from the first lower active region (Fig. 10A-10B);
a lower gate pattern 804 including a first lower gate (lower 804 of 504) and a second lower gate (upper 804 of 504), the first lower gate surrounding the first lower active region (Fig. 10A-10B), and the second lower gate surrounding the second lower active region (Fig. 10A-10B);
a first lower dielectric layer (lower 802 of 504) between the first lower active region and the first lower gate (Fig. 10A-10B);
a second lower dielectric layer (upper 802 of 504) between the second lower active region and the second lower gate (Fig. 10A-10B);
an intermediate insulating layer 312 including a first intermediate insulating layer and a second intermediate insulating layer, the first intermediate insulating layer (low 312) on the first lower active region, and the second intermediate insulating layer (upper 312) on the second lower active region (Fig. 10A-10B);
an upper active region 110 including a first upper active region (lower 110 of 606) and a second upper active region (upper 110 of 606) (Fig. 10A-10B), the first upper active region on the first intermediate insulating layer, and the second upper active region on the second intermediate insulating layer (Fig. 10A-10B);
an upper gate pattern 1004/(804 of 606) surrounding the upper active region and covering the lower gate pattern (Fig. 2);
a first upper dielectric layer (lower 802 of 606) between the first upper active region and the upper gate pattern (Fig. 10A-10B); and
a second upper dielectric layer (upper 802 of 606) between the second upper active region and the upper gate pattern (Fig. 2), wherein the lower gate pattern 804 surrounds a portion of a side (lower side) surface of the intermediate insulating layer, and the upper gate pattern 1004 surrounds a remaining portion (an upper surface of) the surface side of the intermediate insulating layer (Fig. 10A-10B).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. in view of Smith et al. (US 2022/0122892).
As for claims 5 and 20, Lilak et al. disclose Figs. 1-2B and the related text a stacked integrated circuit device, comprising:
a lower active region 211;
a lower gate pattern 213 surrounding the lower active region and including a protruding portion (upper portion, Fig. 2);
a lower dielectric layer 215 between the lower active region and the lower gate pattern (Fig. 2);
an intermediate insulating layer 257/255 on the lower active region (Fig. 2);
an upper active region 231 on the intermediate insulating layer (Fig. 2);
an upper gate pattern 233 surrounding the upper active region, covering the lower gate pattern (Fig. 2); and
an upper dielectric layer 235 between the upper active region and the upper gate pattern (Fig. 2), wherein a threshold voltage of the upper gate pattern and a threshold voltage of the lower gate pattern are different from each other ([0032]-[0033] of Lilak teach materials of the lower gate pattern and the upper gate pattern, therefore it is capable to have different threshold voltage, also many cases have noted that the provision of a feature of adjustability such as voltage is not a patentable advance. In re Stevens, 101 USPQ 284 (CCPa 1954). See also, In re Brandt 64 F.2d 693, 17 USPQ 295), an upper surface of the lower gate pattern 213 is located lower in a vertical direction than an upper surface of the intermediate insulating layer (Fig. 2), and has a downward shape (Fig. 2), the lower gate pattern 213 surrounding a portion of a side surface of the intermediate insulating layer 257/255.
Lilak et al. do not disclose the upper gate pattern electrically connected to the lower gate pattern; an upper surface of the lower gate pattern has a downward convex shape; and the upper gate pattern surrounding a remaining portion of the side surface of the intermediate insulating layer.
Smith et al. teach in Fig. 26-28 and the related text the upper gate pattern (upper 1710) electrically connected to the lower gate pattern (lower 1710); and the upper gate pattern (upper 1710) surrounding a remaining portion of the side surface of the intermediate insulating layer 599.
Lilak et al. and Smith et al. are analogous art because they both are directed stack integrated circuit devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lilak et al. to include the limitations as taught by Smith et al., in order to improve performance of the device (Smith et al.: see abstract).
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to provide the downward convex shape in Lilak et al., order to achieve the device properties.
Furthermore, the change in shape of the upper surface was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the upper surface was significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 8, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al.
As for claim 8, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 1, wherein the lower gate pattern 213 has an upper surface having a downward shape (Fig. 2).
Lilak et al. do not disclose a downward shape is downward convex shape.
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to provide the downward convex shape in Lilak et al., order to achieve the device properties.
Furthermore, the change in shape of the upper surface was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the upper surface was significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As for claim 9 and 13, Lilak et al. disclose the stacked integrated circuit device as claimed in claim 8, except a difference of height in the upper surface of the lower gate pattern is 1 nm to 10 nm; and a thickness from an upper surface to a lower surface of the intermediate insulating layer is about 20 nm to about 50 nm.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include a difference of height in the upper surface of the lower gate pattern is 1 nm to 10 nm; and a thickness from an upper surface to a lower surface of the intermediate insulating layer is about 20 nm to about 50 nm, in order to optimize the performance of the device.
Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 11 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: “an upper surface of the lower gate pattern decreases in the vertical direction if spaced apart from the intermediate insulating layer in a horizontal direction”, as recited in claim 11; “the first lower gate includes a protruding portion extending from one side of the first lower gate to one side of the second lower gate, and the protruding portion electrically connects the first lower gate and the second lower gate to each other”, as recited in claim 11; “the lower gate pattern and the upper gate pattern are located between the first lower active region and the second lower active region, and the upper gate pattern is located between the first upper active region and the second upper active region”, as recited in claim 18; and “the first lower gate and the second lower gate each have an upper surface having curvature”, as recited in claim 19
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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