DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species C, Subspecies 2 in the reply filed on 20 May 2026 is acknowledged. The traversal is on the ground that the search can be performed without a serious burden. This is not found persuasive because the species incorporate a variety of configurations and bonding options that require separate and distinct search characteristics.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al (US 20190279919 A1, hereinafter “Xu”). in view of Bakeman et al (US 4506436, hereinafter “Bakeman”).
Regarding Claim 1 - Xu discloses a semiconductor package comprising: a package substrate (104 [0019] and Fig. 1A); and a first semiconductor chip on the package substrate (108a [0019] and Fig. 1A).
Xu fails to disclose the first semiconductor chip including a first inactive layer and a first active layer, wherein the first inactive layer includes a high-density region, and the high-density region of the first inactive layer has a higher density than densities of other regions of the first inactive layer.
However, Bakeman discloses the first semiconductor chip including a first inactive layer (buried layer and substrate, Bakeman column 5, line 65 to column 6, line 3, and 16 and 10 in Fig. 1) and a first active layer (e.g. IGFET devices, Bakeman column 10, lines 4-8 and Fig. 1), wherein the first inactive layer includes a high-density region (16, Bakeman column 10, lines 33-40 and Fig. 2, as well as column 11, line 67 to column 12, line 10, can be n-type doped instead of p-type, Bakeman column 12, lines 11-17, and known n-type impurities are heavier than silicon (atomic weight (AW) 28), including P (AW 31), As (AW 75), and Sb (AW 122)), and the high-density region of the first inactive layer has a higher density than densities of other regions of the first inactive layer (e.g. three orders of magnitude greater than the substrate, Bakeman column 12, lines 3-7, and Fig. 2).
Bakeman discloses a semiconductor device with a buried layer for alpha particle protection compatible with the package of Xu. Bakeman teaches a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics (Bakeman column 11, lines 15-19). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Xu and Bakeman to incorporate a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics.
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Regarding Claim 2 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses the first active layer is spaced apart from the package substrate and the first inactive layer is between the package substrate and the first active layer (Bakeman column 11, lines 15-19).
Regarding Claim 3 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses the high-density region of the first inactive layer is spaced apart from the first active layer (Bakeman column 9, lines 53-57).
Regarding Claim 4 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses the high-density region of the first inactive layer extends in a direction parallel to a lower surface of the first inactive layer (16 runs parallel to bottom of 10, Bakeman Fig. 1).
Regarding Claim 5 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses a thickness of the high-density region is about 3 µm to about 7 µm (1 to 10 microns, which is an overlapping range, making the claimed range prima facie obvious. See MPEP 2144.05(I)).
Regarding Claim 6 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman fails to expressly disclose a thickness of the first semiconductor chip is about 40 µm to about 60 µm.
However, Xu teaches the total package containing multiple stacked chips covered in molding compound can be 800 µm thick, for example (XU [0036]). The semiconductor chip stack in Fig. 1A (Xu [0019]) shows an example of six chips high, with molding compound constituting some of the height. Combined, these numbers suggest the mean chip thickness could be less than about 130 µm, consistent with the claimed range of 40-60 µm. It is prima facie obvious that the first semiconductor chip could be tens of microns thick as a result of routine optimization. See MPEP 2144.05(II). Therefore, the claimed range of 40-60 µm would have been an obvious conclusion to one of ordinary skill in the art prior to the effective filing date of the claimed invention.
Regarding Claim 7 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses the high-density region is doped with high-density impurities having a higher density than silicon (Any n-type dopant, Bakeman column 12, lines 11-17).
Regarding Claim 8 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip (112, Xu [0027] and Fig. 1A).
Regarding Claim 9 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses a density of the high-density region of the first semiconductor chip gradually decreases in a direction away from the package substrate (Distribution tail toward active region, Bakeman Fig. 2).
Regarding Claim 10 - Xu modified by Bakeman discloses all the limitations of claim 1.
The combination of Xu and Bakeman further discloses a second semiconductor chip on the first semiconductor chip (108b, Xu [0019] and Fig. 1A).
Regarding Claim 11 - Xu modified by Bakeman discloses all the limitations of claim 10.
The combination of Xu and Bakeman further discloses the second semiconductor chip includes a second active layer and a second inactive layer, and the second inactive layer has a constant density (Xu states the chips can be “...any ... appropriate type of semiconductor chip”, and many modern chips with active areas on one surface have a homogeneous inactive region (i.e. substrate) below that. For example, the inactive region of Bakeman Fig. 2 without the buried layer having a constant dopant concentration of 1E15 cm-3, and therefore constant density, versus depth).
Regarding Claim 12 - Xu modified by Bakeman discloses all the limitations of claim 11.
The combination of Xu and Bakeman fails to expressly disclose a density of the second inactive layer is lower than a density of the high-density region of the first inactive layer.
However, a second semiconductor chip without the intentionally placed highly doped inactive layer is closer to the density of silicon, having a lower concentration of dopant (e.g. 1E15 cm-3 background as in Bakeman Fig. 2). Furthermore, as all n-type dopants (P (atomic weight (AW) 31), As (AW 75), and Sb (AW 122)) have higher mass than silicon (AW 28), the density of the doped region increases with increasing dopant concentration. Likewise, a lower concentration of dopant in an n-type region will result in lower density, closer to undoped silicon. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that a chip without the intentional heavily doped buried layer (i.e. the second inactive layer) will have an inactive layer density lower than the density of an inactive layer containing a highly doped buried layer with an n-type dopant (i.e. the first inactive layer).
Regarding Claim 13 - Xu modified by Bakeman discloses all the limitations of claim 10.
The combination of Xu and Bakeman fails to expressly disclose the second semiconductor chip includes a second active layer and a second inactive layer, the second inactive layer includes a second high-density region, and a density of the second high-density region of the second inactive layer is higher than densities of other regions of the second inactive layer.
However, the second semiconductor chip including a second active layer and a second inactive layer, the second inactive layer includes a second high-density region, and a density of the second high-density region of the second inactive layer is higher than densities of other regions of the second inactive layer represents a duplication of parts from the first semiconductor chip. See MPEP 2144.04(VI)(B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider duplicating the high density region of the inactive layer in the first semiconductor chip in another semiconductor chip for the same benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics.
Regarding Claim 14 - Xu modified by Bakeman in view of MPEP 2144.04(VI)(B) discloses all the limitations of claim 13.
The combination of Xu and Bakeman further discloses the second active layer is spaced apart from the first active layer (Stacking chips face up (away from package substrate) is within the description given by Xu [0021], which separates the active areas of first and second chip by the inactive region of the second chip), and the second inactive layer is between the first active layer and the second active layer (Bakeman column 9, lines 53-57).
Regarding Claim 15 - Xu modified by Bakeman in view of MPEP 2144.04(VI)(B) discloses all the limitations of claim 14.
The combination of Xu and Bakeman further discloses the high-density region of the second inactive layer is not in contact with the first active layer and the second active layer (16 well below second active area containing 14 and 18 in Bakeman Fig. 1, and separated by 10 from the first active area below).
Regarding Claim 16 - Xu discloses a redistribution structure (104 [0019] and Fig. 1A); and a semiconductor chip on the redistribution structure (108a [0019] and Fig. 1A).
Xu fails to disclose the semiconductor chip including an inactive layer and an active layer, wherein the inactive layer includes a buried doped region, the buried doped region is doped with high-density impurities, and a density of the high-density impurities is higher than silicon.
However, Bakeman discloses the semiconductor chip including an inactive layer (buried layer and substrate, Bakeman column 5, line 65 to column 6, line 3, and 16 and 10 in Fig. 1) and an active layer (e.g. IGFET devices, Bakeman column 10, lines 4-8 and Fig. 1), wherein the inactive layer includes a buried doped region (16, Bakeman column 10, lines 33-40 and Fig. 2, as well as column 11, line 67 to column 12, line 10), the buried doped region is doped with high-density impurities, and a density of the high-density impurities is higher than silicon (Can be n-type doped instead of p-type, Bakeman column 12, lines 11-17, and known n-type impurities are heavier than silicon (atomic weight (AW) 28), including P (AW 31), As (AW 75), and Sb (AW 122)).
Bakeman discloses a semiconductor device with a buried layer for alpha particle protection compatible with the package of Xu. Bakeman teaches a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics (Bakeman column 11, lines 15-19). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Xu and Bakeman to incorporate a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics.
Regarding Claim 17 - Xu modified by Bakeman discloses all the limitations of claim 16.
The combination of Xu and Bakeman further discloses the buried doped region is in the inactive layer and spaced apart from the active layer (Bakeman column 9, lines 53-57 and Fig. 1).
Regarding Claim 18 - Xu modified by Bakeman discloses all the limitations of claim 16.
The combination of Xu and Bakeman further discloses a through-via passing through at least a portion of the semiconductor chip (Xu [0021]), wherein the active layer is spaced apart from the redistribution structure (Active area denoted by 14 and 18 in Bakeman Fig. 1 is spaced apart from the other side of the chip and redistribution structure by 16 and 10), and the through-via passes through the buried doped region of the inactive layer and is configured to electrically connect the active layer and the redistribution structure (Xu [0021]).
Regarding Claim 19 - Xu modified by Bakeman discloses all the limitations of claim 16.
The combination of Xu and Bakeman further discloses a horizontal width of the buried doped region is equal to a horizontal width of the active layer (16 just as wide as 14+18, Bakeman Fig. 1).
Regarding Claim 20 - Xu discloses a semiconductor package comprising: a package substrate (104 [0019] and Fig. 1A); a first semiconductor chip on the package substrate (108a [0019] and Fig. 1A); and a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip (112, Xu [0027] and Fig. 1A).
Xu fails to disclose the first semiconductor chip includes a first inactive layer and a first active layer, wherein the first inactive layer includes a high-density region doped with high-density impurities having a higher density than silicon, a density of the high-density region of the first inactive layer is higher than densities of other regions of the first inactive layer, the high-density region is spaced apart from the first active layer and is between the package substrate and the first active layer, and a concentration of the high-density impurities doped in the high-density region decreases in a direction toward the first active layer.
However, Bakeman discloses the first semiconductor chip includes a first inactive layer (buried layer and substrate, Bakeman column 5, line 65 to column 6, line 3, and 16 and 10 in Fig. 1) and a first active layer (e.g. IGFET devices, Bakeman column 10, lines 4-8 and Fig. 1), wherein the first inactive layer includes a high-density region doped with high-density impurities having a higher density than silicon (16, Bakeman column 10, lines 33-40 and Fig. 2, as well as column 11, line 67 to column 12, line 10, can be n-type doped instead of p-type, Bakeman column 12, lines 11-17, and known n-type impurities are heavier than silicon (atomic weight (AW) 28), including P (AW 31), As (AW 75), and Sb (AW 122)), a density of the high-density region of the first inactive layer is higher than densities of other regions of the first inactive layer (as seen by impurity concentration in Bakeman Fig. 2), the high-density region is spaced apart from the first active layer and is between the package substrate and the first active layer (Bakeman column 9, lines 53-57, and column 11, lines 15-19, and Fig. 1), and a concentration of the high-density impurities doped in the high-density region decreases in a direction toward the first active layer (Distribution tail toward active region, Bakeman Fig. 2).
Bakeman discloses a semiconductor device with a buried layer for alpha particle protection compatible with the package of Xu. Bakeman teaches a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics (Bakeman column 11, lines 15-19). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Xu and Bakeman to incorporate a heavily doped buried layer substantially deeper than the active region for the benefit of protecting against alpha particle radiation while having little effect on device electrical characteristics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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