DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Amendment
The amendment filed May 8, 2026 has been entered. Claims 1, 3-4, 6-19, and 21-22 remain pending in this application. Claims 11-12 and 14-19 drawn to non-elected invention have been withdrawn. Claims 2, 5, and 20 cancelled at applicant’s request. Claim 1 has been amended. Claims 21-22 have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 6-10, 13, and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0198111 A1 to Yusuke Higashi (hereafter Higashi) in view of US 9,558,804 B2 to Stefan Ferdinand Müller (hereafter Müller), US 8,542,535 B2 to Deepanshu Dutta, et al. (hereafter Dutta), and US 8,988,937 B2 to Mohan Dunga, et al. (hereafter Dunga).
Regarding Independent Claim 1, Higashi discloses a memory device comprising:
a first string (First string NS and SU0: Higashi, Figure 3) including
a first select transistor (First select transistor ST1/SU0: Higashi, Figure 3),
a second select transistor (Second select transistor ST2/SU0: Higashi, Figure 3), and
a plurality of first memory cells (Plurality of memory cells MT0-MT7 in SU0: Higashi, Figure 3)
coupled in series between the first select transistor and the second select transistor (Memory cells MT0-MT7 coupled in series between select transistors ST1 and ST2: Higashi, Figure 3),
the plurality of first memory cells each including a first ferroelectric transistor (Disclosing memory cells MT0-MT7 may be ferroelectric transistors: Higashi, ¶[0024]);
a second string (Second string SU11: Higashi, Figure 3) including
a third select transistor (Third select transistor ST1/SU1: Higashi, Figure 3),
a fourth select transistor (Fourth select transistor ST2/SU1: Higashi, Figure 3), and
a plurality of second memory cells (Plurality of memory cells MT0-MT7/SU0: Higashi, Figure 3)
coupled in series between the third select transistor and the fourth select transistor (Memory cells coupled in series between select transistors: Higashi, Figure 3),
the plurality of second memory cells each including a second ferroelectric transistor (Disclosing memory cells may be ferroelectric transistors: Higashi, ¶[0024]);
a first select gate line (First select gate line SGD0: Higashi, Figure 3) coupled to a gate of the first select transistor (First select gate line SGD0 coupled to the first select transistor ST1/SU0: Higashi, Figure 3);
a second select gate line (Second select gate line SGD1: Higashi, Figure 3) coupled to a gate of the third select transistor (Second select gate line SGD1 coupled to the third select transistor ST1/SU1: Higashi, Figure 3);
a plurality of word lines (A plurality of word lines WL0-WL7: Higashi, Figure 3)
coupled to gates of the plurality of first memory cells and to gates of the plurality of second memory cells (Wordlines connected to gates of first and second memory cells: Higashi, Figure 3);
a bit line (Bitline BL0: Higashi, Figure 3) coupled to one end of the first select transistor and one end of the third select transistor (Bitline BL0 coupled to one end of first and third select transistors: Higashi, Figure 3);
a source line (Source line CELSRC: Higashi, Figure 3) coupled to one end of the second select transistor and one end of the fourth select transistor (Source line CELSRC connected to one end of second and fourth select transistors: Higashi, Figure 3); and
a circuit that controls an erase sequence (A controlling memory circuit is inherent in any memory array operation), wherein in the erase sequence
for a first selected memory cell among the plurality of first memory cells (First selected memory cell: Higashi, Figure 3) and
a second selected memory cell among the plurality of second memory cells (Second selected memory cell: Higashi, Figure 3)
in which the first and second selected memory cells are
coupled to a first selected word line among the plurality of word lines (Cells coupled to the first selected word line: Higashi, Figure 3) and
coupled to the bit line via the first and second select transistors (Cells coupled to the bit line via the first and second select transistors: Higashi, Figure 3).
Higashi does not disclose specific voltage arrangements as is described in the further limitations of Claim 1. Müller, however, discloses a ferroelectric memory array wherein:
the circuit is configured to:
apply a first voltage (A first voltage VE/3: Müller, col.10:39-42) having a positive voltage (VE being a positive value: Müller, col.10:37) value to the bit line (First voltage applied to a bit line: Müller, col.10:39-42);
apply a third voltage (A third voltage 2VE/3: Müller, col.10:43-45) having a positive voltage value higher than the first voltage (A voltage higher than a positive voltage is inherently positive)
to a plurality of first non-selected word lines among the plurality of word lines (Applying the third voltage to non-select word lines: Müller, col.10:43-45); and
apply a fourth voltage (A fourth voltage 0V: Müller, col.10:43) lower than the first voltage (A voltage of 0V is inherently less than any positive voltage)
to the first selected word line among the plurality of word lines (Fourth voltage applied to select word lines: Müller, col.10:42-43).
Müller teaches the appropriate application of voltages to the memory array allows for erasing selected memory cells without parasitic current flow on neighboring lines and without changing the states of neighboring cells (Müller, col.10:28-31). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the strategic erase method of Müller with the memory array architecture of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of ferroelectric memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Higashi discloses select gate transistors ST1 and ST2 (Higashi, Figure 3), but does not disclose specific voltages applied to these transistors except in broad terms. Müller does not disclose select gate transistors, at all. Dutta, however, discloses a ferroelectric memory array as in Higashi and Müller, with select gate transistors wherein the controller is configured to:
apply a second voltage (Disclosing a second voltage: Dutta, Figure 9A) having a positive voltage value higher than the first voltage
to each of the first select gate line and the second select gate line (Disclosing the bit line is left to float while select gate line is driven to an optimal voltage approaching VMAX: Dutta, col.10:9-16).
Dutta discloses controlling the select gate voltage relative to the bit line and other voltages helps minimize wear on the select gate oxide, at the expense of increasing power consumption (Dutta, col.10:17-25). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the controlled select gate voltage with the memory array architecture of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory array erase operations and the combination of known inventions with predictable results is obvious and not patentable.
The prior art previously specified does not disclose each of the first and third select transistors being turned on by a potential difference between the first voltage and the second voltage, and the first voltage is transferred to a channel region of each of the first and second selected memory cells via the first and third select transistors in an on state. Dunga, however, discloses a pre-charge operation in a memory array wherein:
each of the first and third select transistors is turned on (Select gate transistors turned on with a Vth of 1V: Dunga, col.15:15:27)
by a potential difference between the first voltage and the second voltage (The select gate Vth of 1V being exceeded by the difference between the bit line voltage [Vbl = 2.5V] and the select gate voltage[Vsgd = 5]: Dunga, col.15:23-27), and
the first voltage is transferred to a channel region of each of the first and second selected memory cells via the first and third select transistors in an on state (The select gate transistor being turned on, allowing the channel to be driven by the bitline voltage: Dunga, col.15:29-31).
Dunga teaches this pre-charge operation is most useful during programming operations where the channel of storage elements are erased (Dunga, col.15:29-24). However, it also further acknowledges such a pre-charge operation may weakly boost the channel (Dunga, col.15:40-41), may be used to partially pre-charge the line (Dunga, col.15:49-53), and further describes increasing the wordline voltages to allow deeper penetration of the pre-charge voltage (Dunga, col.16:10-23) and therefore the pre-charge method is effective even for a NAND string that is partially programmed (Dunga, abstract). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the pre-charge method of Dunga with memory array architecture of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of pre-charging memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 3, Müller discloses the memory device according to claim 1, wherein
a potential of the gates of the first and second selected memory cells coupled to the first selected word line (VERASE, applied to the gate in a negative gate erase operation: Müller, Figure1) is lower than a potential of channel edges (Channel edges held to ground: Müller, Figure 1) of the first and second selected memory cells coupled to the first selected word line (VERASE expressly disclosed as being less than ground: Müller, Figure 1).
Regarding Claim 4, Dutta discloses the memory device according to claim 1, wherein in the erase sequence,
a potential of the gate of the first select transistor (The gate potential raised to an erase voltage: Dutta, col.7:3-4) is higher than a potential of the one end of the first select transistor (The bitline voltage being left to float, being less than the erase voltage: Dutta, col.7:9-11), and
a potential of the gate of the third select transistor (The gate potential raised to an erase voltage: Dutta, col.7:3-4) is higher than a potential of the one end of the third select transistor (The bitline voltage being left to float, being less than the erase voltage: Dutta, col.7:9-11).
Regarding Claim 6, Müller discloses the memory device according to claim 1, wherein in the erase sequence,
potentials of the gates of the plurality of first and second memory cells coupled to the plurality of first non-selected word lines (Showing unselected wordlines held at VP/3: Müller, Figure B; Note, VP is expressly greater than ground) are higher than potentials at channel edges of the plurality of first and second memory cells coupled to the plurality of first non-selected word lines (Potential at channel edges of unselected memory cells held at ground: Müller, Figure 7B).
Regarding Claim 7, Dutta discloses the memory device according to claim 1, wherein in the erase sequence,
the plurality of first and second memory cells coupled to the plurality of first non-selected word lines are turned on (Disclosing keeping all memory cells conductive during erase operations: Dutta, col.11:25-35).
Regarding Claim 8, Dutta discloses the memory device according to claim 1, wherein
the third voltage is equal to the second voltage (Showing the select gate lines and unselected wordlines driven to the same voltage: Dutta, col.11:25-30).
Regarding Claim 9, Müller discloses the memory device according to claim 1, wherein
the fourth voltage is a ground voltage (Disclosing the select word line voltage is ground: Müller, 10:50-51).
Regarding Claim 10, Higashi discloses the memory device according to claim 1, further comprising
a third select gate line (A third select gate line SGS: Higashi, Figure 3) coupled to gates of the second and fourth select transistors (Coupled to the second and forth select transistors: Higashi, Figure 3),
wherein in the erase sequence, the circuit is configured to:
apply the first voltage to the source line (The same voltage applied to both bit and source lines: Müller, Figure 3A; Note, this configuration is discloses standard in the art); and
apply the second voltage to the third select gate line (The same voltage, VSG, applied to both select gates SGS and SGD: Higashi, Figure 8)
Regarding Claim 13, Müller discloses the memory device according to claim 1, wherein
each of the first and second ferroelectric transistors includes hafnium oxide (The ferroelectric transistors including Hafnium Oxide: Müller, col.3:65-66).
Regarding New Claim 21, Müller discloses the memory device according to claim 1, wherein the circuit is configured to:
supply an erase pulse to the first and second selected memory cells, the erase pulse having a negative polarity based on a potential difference between the first voltage and the fourth voltage (Describing applying a negative voltage to the gate terminal of the memory cell being common: Müller, col.6:21-25); and
apply the first voltage to the bit line after the second voltage is applied to each of the first and second select gate lines (Select gate voltage Vsl being applied before bit line voltage is applied: Dunga, Figures 9A & 9B) and
the third voltage is applied to each of the plurality of first non-selected word lines (Applying the third voltage to non-select word lines: Müller, col.10:43-45).
Regarding New Claim 22, Müller discloses a memory device according to claim 21, wherein
the erase pulse is applied
between a gate and a channel region of the first ferroelectric transistor in the first selected memory cell (The erase pulse being applied between the gate and the bulk region of the selected memory cell: Müller, Figure 1) and
between a gate and a channel region of the second ferroelectric transistor in the second selected memory cell (The erase pulse being applied between the gate and the bulk region of the selected memory cell: Müller, Figure 1),
a potential of the channel region of each of the first and second ferroelectric transistors in the first and second selected memory cells being higher than a potential of the gate of each of the first and second ferroelectric transistors in the first and second selected memory cells (The potential of the bulk region being higher than the potential applied to the gate: Müller, Figure 1).
Response to Arguments
Applicant's arguments filed May 28, 2026 have been fully considered but they are not persuasive.
Applicant argues the cited prior art, specifically Dutta, fails to disclose the first voltage being applied to the bit line, instead stating correctly the bit line is made to float (Applicant Arguments/Remarks, page 11, ¶1). Dutta describes charging the select gate to a high value, described as exceeding the sum of the drive voltage (bit line voltage) and the threshold voltage of the pass gate (Dutta, col.9:45-51). As such, the voltage applied to the gate necessarily exceeds the voltage applied to the bit line, even after the bit line is left to float.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230034752 A1 to Sheyang Ning: Disclosing a specific and sequential application of erase voltages during an erase sequence in a ferroelectric memory array.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 06/11/2026
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