DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed January 30, 2026 has been entered. Claims 1 and 3-20 remain pending in this application. Claims 11-12 and 14-19 drawn to non-elected invention have been withdrawn. Claim 2 has been cancelled at applicant’s request. Claims 1 and 3 have been amended. Claim 20 has been added. No new matter has been added.
Applicant’s amendments to the Specification has overcome the title rejection previously set forth in the Non-Final Office Action mailed October 31, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding New Claim 20, it states: The memory device according to claim 1, wherein the erase pulse is generated at channel regions of the first and second selected memory cells. Claim 1 discloses precise voltages applied in a precise order, specifically a second voltage applied to the first and second select gate lines and a third voltage applied to non-selected word lines, only then applying the first voltage to the bit line. This order inherently results in an erase pulse being generated at the channel regions of the selected memory cells. Therefore, new Claim 20 fails to further limit the claim from which it depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 3-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0198111 A1 to Yusuke Higashi (hereafter Higashi) in view of US 9558804 B2 to Stefan Ferdinand Müller (hereafter Müller) and further in view of US 8,542,535 B2 to Deepanshu Dutta, et al. (hereafter Dutta).
Regarding Independent Claim 1, Higashi discloses a memory device comprising:
a first string (First string NS and SU0: Higashi, Figure 3) including
a first select transistor (First select transistor ST1/SU0: Higashi, Figure 3),
a second select transistor (Second select transistor ST2/SU0: Higashi, Figure 3), and
a plurality of first memory cells (Plurality of memory cells MT0-MT7 in SU0: Higashi, Figure 3)
coupled in series between the first select transistor and the second select transistor (Memory cells MT0-MT7 coupled in series between select transistors ST1 and ST2: Higashi, Figure 3),
the plurality of first memory cells each including a first ferroelectric transistor (Disclosing memory cells MT0-MT7 may be ferroelectric transistors: Higashi, ¶[0024]);
a second string (Second string SU11: Higashi, Figure 3) including
a third select transistor (Third select transistor ST1/SU1: Higashi, Figure 3),
a fourth select transistor (Fourth select transistor ST2/SU1: Higashi, Figure 3), and
a plurality of second memory cells (Plurality of memory cells MT0-MT7/SU0: Higashi, Figure 3)
coupled in series between the third select transistor and the fourth select transistor (Memory cells coupled in series between select transistors: Higashi, Figure 3),
the plurality of second memory cells each including a second ferroelectric transistor (Disclosing memory cells may be ferroelectric transistors: Higashi, ¶[0024]);
a first select gate line (First select gate line SGD0: Higashi, Figure 3) coupled to a gate of the first select transistor (First select gate line SGD0 coupled to the first select transistor ST1/SU0: Higashi, Figure 3);
a second select gate line (Second select gate line SGD1: Higashi, Figure 3) coupled to a gate of the third select transistor (Second select gate line SGD1 coupled to the third select transistor ST1/SU1: Higashi, Figure 3);
a plurality of word lines (A plurality of word lines WL0-WL7: Higashi, Figure 3)
coupled to gates of the plurality of first memory cells and to gates of the plurality of second memory cells (Wordlines connected to gates of first and second memory cells: Higashi, Figure 3);
a bit line (Bitline BL0: Higashi, Figure 3) coupled to one end of the first select transistor and one end of the third select transistor (Bitline BL0 coupled to one end of first and third select transistors: Higashi, Figure 3);
a source line (Source line CELSRC: Higashi, Figure 3) coupled to one end of the second select transistor and one end of the fourth select transistor (Source line CELSRC connected to one end of second and fourth select transistors: Higashi, Figure 3); and
an erase sequence
for a first selected memory cell among the plurality of first memory cells (First selected memory cell: Higashi, Figure 3) and
a second selected memory cell among the plurality of second memory cells (Second selected memory cell: Higashi, Figure 3)
in which the first and second selected memory cells are
coupled to a first selected word line among the plurality of word lines (Cells coupled to the first selected word line: Higashi, Figure 3) and
coupled to the bit line via the first and second select transistors (Cells coupled to the bit line via the first and second select transistors: Higashi, Figure 3).
Higashi does not disclose and erase sequence with the specific voltage arrangements as is described in the further limitations of Claim 1. Müller, however, discloses a ferroelectric memory array wherein:
a circuit that controls an erase sequence (A controlling memory circuit is inherent in any memory array operation), wherein in the erase sequence the circuit is configured to:
apply a first voltage (A first voltage VE/3: Müller, col.10:39-42) having a positive voltage (VE being a positive value: Müller, col.10:37) value to the bit line (First voltage applied to a bit line: Müller, col.10:39-42);
apply a third voltage (A third voltage 2VE/3: Müller, col.10:43-45) having a positive voltage value higher than the first voltage (A voltage higher than a positive voltage is inherently positive)
to a plurality of first non-selected word lines among the plurality of word lines (Applying the third voltage to non-select word lines: Müller, col.10:43-45); and
apply a fourth voltage (A fourth voltage 0V: Müller, col.10:43) lower than the first voltage (A voltage of 0V is inherently less than any positive voltage)
to the first selected word line among the plurality of word lines (Fourth voltage applied to select word lines: Müller, col.10:42-43),
supply an erase pulse to the first and second selected memory cells,
the erase pulse having a negative polarity based on a potential difference between the first voltage and the fourth voltage (Describing a “common way to erase a FeFET” being to apply a negative voltage to the gate terminal of cells to be erased: Müller, col.6:21-25), and
apply the first voltage to the bit line after the second voltage is applied to each of the first and second select gate lines and the third voltage is applied to each of the plurality of first non-selected word lines (Applying bitline erase voltage after having already set the wordline/bulk select voltages: Müller, col.10:11-14).
Müller teaches the appropriate application of voltages to the memory array allows for erasing selected memory cells without parasitic current flow on neighboring lines and without changing the states of neighboring cells (Müller, col.10:28-31). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the strategic erase method of Müller with the memory array architecture of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of ferroelectric memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Higashi discloses select gate transistors ST1 and ST2 (Higashi, Figure 3), but does not disclose specific voltages applied to these transistors except in broad terms. Müller does not disclose select gate transistors, at all. Dutta, however, discloses a ferroelectric memory array as in Higashi and Müller, with select gate transistors wherein the controller is configured to:
apply a second voltage (Disclosing a second voltage: Dutta, Figure 9A) having a positive voltage value higher than the first voltage
to each of the first select gate line and the second select gate line (Disclosing the bit line is left to float while select gate line is driven to an optimal voltage approaching VMAX: Dutta, col.10:9-16);
Dutta discloses controlling the select gate voltage relative to the bit line and other voltages helps minimize wear on the select gate oxide, at the expense of increasing power consumption (Dutta, col.10:17-25). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the controlled select gate voltage with the memory array architecture of Higashi, with a reasonable expectation of success. Both inventions are well known in the field of memory array erase operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 3, Müller discloses the memory device according to claim 1, wherein
a potential of the gates of the first and second selected memory cells coupled to the first selected word line (VERASE, applied to the gate in a negative gate erase operation: Müller, Figure1) is lower than a potential of channel edges (Channel edges held to ground: Müller, Figure 1) of the first and second selected memory cells coupled to the first selected word line (VERASE expressly disclosed as being less than ground: Müller, Figure 1).
Regarding Claim 4, Dutta discloses the memory device according to claim 1, wherein in the erase sequence,
a potential of the gate of the first select transistor (The gate potential raised to an erase voltage: Dutta, col.7:3-4) is higher than a potential of the one end of the first select transistor (The bitline voltage being left to float, being less than the erase voltage: Dutta, col.7:9-11), and
a potential of the gate of the third select transistor (The gate potential raised to an erase voltage: Dutta, col.7:3-4) is higher than a potential of the one end of the third select transistor (The bitline voltage being left to float, being less than the erase voltage: Dutta, col.7:9-11).
Regarding Claim 5, Dutta discloses the memory device according to claim 1, wherein in the erase sequence,
the first and third select transistors are turned on (Disclosing the voltage applied to the select gates being optimized for erase operations: Dutta, col.10:9-16).
Regarding Claim 6, Müller discloses the memory device according to claim 1, wherein in the erase sequence,
potentials of the gates of the plurality of first and second memory cells coupled to the plurality of first non-selected word lines (Showing unselected wordlines held at VP/3: Müller, Figure B; Note, VP is expressly greater than ground) are higher than potentials at channel edges of the plurality of first and second memory cells coupled to the plurality of first non-selected word lines (Potential at channel edges of unselected memory cells held at ground: Müller, Figure 7B).
Regarding Claim 7, Dutta discloses the memory device according to claim 1, wherein in the erase sequence,
the plurality of first and second memory cells coupled to the plurality of first non-selected word lines are turned on (Disclosing keeping all memory cells conductive during erase operations: Dutta, col.11:25-35).
Regarding Claim 8, Dutta discloses the memory device according to claim 1, wherein
the third voltage is equal to the second voltage (Showing the select gate lines and unselected wordlines driven to the same voltage: Dutta, col.11:25-30).
Regarding Claim 9, Müller discloses the memory device according to claim 1, wherein
the fourth voltage is a ground voltage (Disclosing the select word line voltage is ground: Müller, col.10:50-51).
Regarding Claim 10, Higashi discloses the memory device according to claim 1, further comprising
a third select gate line (A third select gate line SGS: Higashi, Figure 3) coupled to gates of the second and fourth select transistors (Coupled to the second and forth select transistors: Higashi, Figure 3),
wherein in the erase sequence, the circuit is configured to:
apply the first voltage to the source line (The same voltage applied to both bit and source lines: Müller, Figure 3A; Note, this configuration is discloses standard in the art); and
apply the second voltage to the third select gate line (The same voltage, VSG, applied to both select gates SGS and SGD: Higashi, Figure 8)
Regarding Claim 13, Müller discloses the memory device according to claim 1, wherein
each of the first and second ferroelectric transistors includes hafnium oxide (The ferroelectric transistors including Hafnium Oxide: Müller, col.3:65-66).
Response to Arguments
Applicant's arguments filed January 30, 2026 have been fully considered but they are not persuasive.
Applicant’s primary argument amounts to a piecemeal analysis of the individual pieces of prior art. Applicant argues Higashi teaches the configuration of the application but fails to show control circuitry controlling the erase sequence or the specific voltages applied during the erase sequence (Applicant’s Response, p.11¶1). Müller, which does show such control circuitry and erase sequence, nevertheless fails to disclose the use of a second voltage as described in the application (Applicant’s Response, p.11¶2). Dutta, meanwhile, describes the second voltage, but applies it to a memory array with a different configuration (Applicant’s Response, p.11¶3). All of these points are acknowledged in the prior non-final rejection dated October 31, 2025. That analysis does not depend on any one piece of prior art individually but instead relies on the combination of references. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant also argues there is no motivation to combine Dutta with the other cited prior art as Dutta is directed to a NAND-flash memory device rather than a ferroelectric memory device (Applicant’s Response, p.11¶3). There is considerable overlap between NAND-flash memory arrays and ferroelectric memory arrays (Describing the instant device as a NAND type flash memory including ferroelectric memory cells: Higashi, ¶[0024]) and the scope of analogous art is to be construed broadly (MPEP § 2141.01(a)). Further, there is no rigid requirement that relevant prior art be from a precisely analogous art provided there exists some adequate reason to combine (See MPEP § 2141.01(a) stating: The Supreme Court’s decision in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), did not change the test for analogous art as stated in Bigio. Under Bigio, a reference need not be from the same field of endeavor as the claimed invention in order to be analogous art. Bigio, 381 F.3d at 1325, 72 USPQ2d at 1212.).
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230034752 A1 to Sheyang Ning: Disclosing a specific and sequential application of erase voltages during an erase sequence in a ferroelectric memory array.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 02/27/2026