Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hartung (US 20150001700).
Regarding claim 1, Hartung discloses a power module, comprising:
a substrate (the substrate 102, Fig. 1) comprising a patterned metallization (the metallized top side 106) on an electrically insulative body (the insulative body 108; paragraph 16);
a plurality of first power semiconductor dies (the left side power semiconductor die 110) attached to a first metallic island (the left side 106) of the patterned metallization;
a plurality of second power semiconductor dies (the right side power semiconductor die 110) attached to a second metallic island (the right side 106) of the patterned metallization;
a mold compound (the potting compound 124) at least partly embedding the substrate, the first power semiconductor dies, and the second power semiconductor dies; and a multilevel metallic frame (the plurality of the electrical connections 120; paragraph 18) partly embedded in the mold compound and disposed over the substrate, wherein the multilevel metallic frame comprises a plurality of power terminals (the exposed side of 120) exposed at a side of the mold compound that faces away from the patterned metallization and that transition between two or more different levels (120 is going through several levels such as 116, 126, 124, 106) to electrically interconnect the first power semiconductor dies (110) and the second power semiconductor dies (110) in a half bridge or full bridge configuration (the bridge through the middle 106).
Regarding claim 3, Hartung discloses the claimed invention as set forth in claim 1. Hartung further suggests the multilevel metallic frame is laterally restricted to a footprint of the substrate.
Regarding claim 24, Hartung discloses the claimed invention as set forth in claim 1. Hartung further suggests the multilevel metallic frame is laterally restricted to a footprint of the mold compound (the footprint of the terminal 120 is within the footprint of the substrate 102).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 4, 14 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hartung (US 20150001700), in view of Martin (US 20190181770).
Regarding claim 2, Hartung discloses the claimed invention as set forth in claim 1.
Hartung does not explicitly disclose the power module has a stray inductance below 5 nH.
Martin teaches the power module has a stray inductance below 5 nH (paragraph 235).
It would have been obvious to one having skill in the art at the effective filing date of the invention to reduce the parasitic inductance in order to increase the effectiveness of the power module.
Regarding claim 4, Hartung discloses the claimed invention as set forth in claim 1.
Hartung does not explicitly disclose the plurality of power terminals of the multilevel metallic frame comprises a first DC terminal, a second DC terminal, and a phase terminal.
Hartung suggests the terminals 120 conduct power, input signal, output signal, etc; paragraph 18.
Martin teaches the terminals are part of a DC circuit, paragraph 110, including a phase terminal, paragraph 120.
It would have been obvious to one having skill in the art at the effective filing date of the invention include DC terminals and phase terminal in the DC circuit in order to complete the DC circuitry of the power module and to connect the power module to the external device.
Regarding claim 14, Hartung, in view of Martin, discloses the claimed invention as set forth in claim 4. Hartung suggests the first DC terminal, the second DC terminal, and the phase terminal each run exposed along the side of the mold compound that faces away from the patterned metallization (the terminals 120 exposed from the potting compound away from the metallization layer).
Regarding claim 15, Hartung, in view of Martin, discloses the claimed invention as set forth in claim 4. Hartung suggests the first DC terminal, the second DC terminal, and the phase terminal each protrude from the side of the mold compound that faces away from the patterned metallization (the terminals 120 exposed from the potting compound away from the metallization layer).
Regarding claim 16, Hartung, in view of Martin, discloses the claimed invention as set forth in claim 4.
Hartung does not explicitly disclose the first DC terminal, the second DC terminal, and the phase terminal each have an exposed screw type, bolt type, press-fit type or rivet type connector at the side of the mold compound that faces away from the patterned metallization.
Martin suggests the terminal 614, Fig. 10, including a screw 634.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common fastener such as a screw in order to secure a terminal to the circuit board.
Allowable Subject Matter
Claims 5 – 13, 17 - 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 4, a combination of limitations that the first DC terminal transitions from a first level to a second level, wherein the second DC terminal transitions from the first level to a third level that is between the first level and the second level, wherein the phase terminal transitions from the first level to the third level and to the second level, wherein at the first level, the first DC terminal, the second DC terminal, and the phase terminal are each uncovered by the mold compound. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 4, a combination of limitations that the mold compound has an undercut in each region where the first DC terminal, the second DC terminal, and the phase terminal are exposed at the side of the mold compound that faces away from the patterned metallization. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 18, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that an additional metallic frame partly embedded in the mold compound and comprising: a first gate terminal protruding from a side face of the mold compound and running along a first edge of the substrate; and a second gate terminal protruding from the side face of the mold compound and running along a second edge of the substrate opposite the first edge, wherein the first gate terminal is electrically connected to a third metallic island of the patterned metallization and the third metallic island is electrically connected to a gate pad of the first power semiconductor dies, wherein the second gate terminal is electrically connected to a fourth metallic island of the patterned metallization and the fourth metallic island is electrically connected to a gate pad of the second power semiconductor dies. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nikitin (US 20230361087) discloses a power module having a substrate, semiconductor dies, and terminals, Fig. 2.
Mohn (US 20180366400) discloses a power module having a substrate, semiconductor dies, and terminals, Fig. 1.
Schulz (US 20090140399) discloses a power module having a substrate, semiconductor dies, and terminals, Fig. 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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