CTNF 18/437,854 CTNF 77428 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Semiconductor Device Having Dot Field Plate Structure”. 07-29 AIA The disclosure is objected to because of the following informalities: The acronym “FP” is not spelled out in the specification. The examiner suggests amending paragraph [0034] to change “dot FP structure” to read, “dot FP (Field Plate) structure” . Appropriate correction is required. 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 Claim s 1 and 5 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of copending Application No. 18/437,906 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because all pertinent limitations in current claim 1 and 5 are recited in claim 8 of the reference application. Therefore, one of ordinary skill in the art would have deemed the invention in current claims 1 and 5 to be an obvious variant of the invention in claim 8 of the reference application. Note the comparison chart below, wherein the differences between the two claims are in bold, underlined text , and similar limitations that are worded differently are shown in italicized, underlined text ) . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 08-35 Claim s 1 and 4 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of copending Application No. 18/438,024 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because all essential limitations in current claim 4 are recited in claim 7 of the reference application. Therefore, one of ordinary skill in the art would have deemed the invention in current claims 1 and 4 to be an obvious variant of the invention in claim 7 of the reference application. Note the comparison chart below, wherein the differences between the two claims are in bold, underlined text , and similar limitations that are worded differently are shown in italicized, underlined text ) . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Current application (18/437,854) US Application No. 18/437,906 A semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first direction and crossing the second direction, a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first electrode region and the second electrode region; a first insulating part including a first insulating region including a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and a second insulating portion located between the first semiconductor region and the first electrode region in the first direction, a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction, and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including a fifth insulating portion located between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions; and a connection part located between the third insulating region and the second insulating part in the second, third, and fourth directions, the connection part electrically connecting the second electrode and the second semiconductor region, the connection part including a first connection part positioned between the third insulating region and the second insulating part in the second, third, and fourth directions, and a second connection part positioned between the third insulating region and the first connection part in the fourth direction. 5. The device according to claim 1 , wherein a lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion. A semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first direction and crossing the second direction, a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first electrode region and the second electrode region; a first insulating part including a first insulating region including a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and a second insulating portion located between the first semiconductor region and the first electrode region in the first direction, a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction, and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including a fifth insulating portion located between the second semiconductor region and the second electrode region in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; and a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions, (for claim 5 of the current application) a lower end of the sixth insulating portion being positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion 8. The device according to claim 1, further comprising: a first connection part located between the third insulating region and the second insulating part in the second and third directions, the first connection part electrically connecting the second electrode and the second semiconductor region ; and a second connection part located between the third insulating region and the first connection part in the fourth direction, the second connection part electrically connecting the second electrode and the second semiconductor region. Current application (18/437,854) US Application No. 18/438,024 A semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first direction and crossing the second direction , a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first electrode region and the second electrode region ; a first insulating part including a first insulating region including a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and a second insulating portion located between the first semiconductor region and the first electrode region in the first direction, a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction, and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including a fifth insulating portion located between the second semiconductor region and the third electrode region in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions; and a connection part located between the third insulating region and the second insulating part in the second, third, and fourth directions, the connection part electrically connecting the second electrode and the second semiconductor region, the connection part including a first connection part positioned between the third insulating region and the second insulating part in the second, third, and fourth directions , and a second connection part positioned between the third insulating region and the first connection part in the fourth direction. 4 . The device according to claim 1, further comprising: a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type. A semiconductor device, comprising: a first electrode; a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type; a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type; a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type; a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region; a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction crossing the first and second directions, the first direction being from the first electrode toward the second electrode, the second direction being perpendicular to the first direction , a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first and second electrode regions ; a first insulating part including a first insulating region including a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and a second insulating portion located between the first semiconductor region and the first electrode region in the first direction; a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction, and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including a fifth insulating portion located between the second semiconductor region and the third electrode region in a fourth direction perpendicular to the first direction, the fourth direction crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction; a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions; a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions; and ( for claim 4 of the current application ) a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type. 7. The device according to claim 1, further comprising: a first connection part located between the third insulating region and the second insulating part in the second and third directions, the first connection part electrically connecting the second electrode and the second semiconductor region ; and a second connection part located between the third insulating region and the first connection part in the fourth direction , the second connection part electrically connecting the second electrode and the second semiconductor region. Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 7-9 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 2, 3 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 2 is allowed primarily because the prior art of record cannot anticipate or render obvious to limitations in this claim when combined with claim 1; Claim 3 is allowed primarily because the prior art of record cannot anticipate or render obvious to limitations in this claim when combined with claim 1; Claim 6 is allowed primarily because the prior art of record cannot anticipate or render obvious to limitations in this claim when combined with claim 1; and Claims 7-9 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim 7: a width of the connection part in the fourth direction being greater than a width of the connection part in the second direction and a width of the connection part in the third direction. The closest prior art are Ichinoseki et al. (US 2021/0083108 A1) and Fujino (US 2023/0307510 A1) that both disclose vertical MOSFETs; however, neither reference suggests a connection part oriented relative to a fourth direction as required by independent claims 1 and 7. In other words, the current application discloses four directions, wherein a fourth direction (D4 in Fig. 4) crosses second (D2) and third (D3) directions and is perpendicular to a first direction (D1); accordingly, a connection part having a structure relative to the fourth direction as required by claims 1 and 7 cannot be anticipated or rendered obvious by the prior art of record . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ichinoseki et al. (US 2021/0083108 A1) and Fujino (US 2023/0307510 A1) disclose vertical MOSFETs comprising a dot field plate structure but do not disclose or suggest a connection part relative to a fourth direction as required by the current invention . Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEX H MALSAWMA/Primary Examiner, Art Unit 2892 Application/Control Number: 18/437,854 Page 2 Art Unit: 2892 Application/Control Number: 18/437,854 Page 3 Art Unit: 2892 Application/Control Number: 18/437,854 Page 4 Art Unit: 2892
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