DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 06/17/2026 is acknowledged. Thusly withdrawing Claims 16-20 from further consideration.
Claims 4-6 are being withdrawn from further consideration as pertaining to the unelected Group I. Claim 4 introduces a horizontal portion of the channel interfacial layer which in light of the specification thusly separates the horizontal portion of the channel structures from the bit line. Claims 5 and 6 inherit this consideration. Therefore Claims 1-3, and 7-15 will be examined.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Min Tae Ryu (US 20220223732 A1) Hereinafter referred to as “Ryu”.
Regarding Claim 1 Ryu teaches
A semiconductor memory device (Fig 9b or 5) comprising:
a bit line (120 Para[0030]) that extends in a first direction (X) on a substrate (100);
a protruded insulating pattern (inner portion of 112 and 116) on the bit line and in a channel trench;
a first channel pattern (130) that extends along sidewalls (left sidewalls of each trench) of the channel trench and includes a first metal oxide (IGZO Para [0039], [0044]); a second channel pattern (130) that extends along the sidewalls (right sidewalls of each trench) of the channel trench, includes the first metal oxide (Para [0039][0044]), and is spaced apart from the first channel pattern in the first direction(X) (Fig 2, 3, and 9b);
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a channel interfacial layer (outer portions of 112 see diagrams) that extends along the sidewalls (left and right sidewalls of each trench) of the channel trench, and is in contact with the first channel pattern and the second channel pattern;
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a first word line (150a) between the first channel pattern and the second channel pattern, and that extends in a second direction (Y) that intersects that first direction (X)(Fig 1);
a second word line (150b fig 9b) between the first channel pattern and the second channel pattern, that extends in the second direction, and is spaced apart from the first word line (spaced part by layer 114) in the first direction(X); and
a first capacitor(170a) and a second capacitor (170b) which are electrically connected to the first channel pattern and the second channel pattern, respectively.
Regarding Claim 2 Ryu teaches
The semiconductor memory device of claim 1,
wherein the first channel pattern (130) and the second channel pattern(130) are in contact (they are in electrical contact and/or in physical contact with each other Fig 9b) with an upper surface of the bit line(120).
Regarding Claim 3 Ryu teaches
The semiconductor memory device of claim 2, wherein the channel interfacial layer (outer portions of 112) includes at least one of a silicon oxide (Para [0035]), a silicon oxynitride, a silicon nitride or a second metal oxide, and wherein the second metal oxide comprises an insulating material.
Regarding Claim 7 Ryu teaches
The semiconductor memory device of claim 1,
wherein the protruded insulating pattern(portions of 112 and now including 116) includes a lower protruded insulating pattern(112) and an upper protruded insulating pattern(116), and wherein the lower protruded insulating pattern is between the bit line (120) and the upper protruded insulating pattern.(116)(Fig.9b)
Regarding Claim 8 Ryu teaches
The semiconductor memory device of claim 1,
wherein the first word line(150a) includes a first portion and a second portion, and wherein a width of the first portion of the first word line (TH31 Fig 3 Para [0051]) in the first direction (X) is less than a width of the second portion of the first word line in the first
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direction.(since the spec teaches
TH31 and the extra portion 112t2
that adds to the width of 15a as
depicted in Fig 1. One can see that
the width of 150a near 112t2 would
be wider than TH31) (see diagram)
Regarding Claim 9 Ryu teaches
The semiconductor memory device of claim 1, further comprising:
a gate isolation pattern (Fig 2 or 9b element 114) on the bit line (120), wherein the gate isolation pattern separates the first word line(150a) and the second word line(150b) from each other, wherein the first channel pattern and the second
channel pattern are connected to each other by a connection channel pattern (at least a portion of the horizontal portion of 130), and wherein the gate isolation pattern(114) is on the connection channel pattern.(Fig 9b or 2)
Regarding Claim 10 Ryu teaches
The semiconductor memory device of claim 1,
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further comprising: a gate insulating layer (140a) between the first channel pattern (130 on the left of the trench) and the first word line(150a), wherein a height from an upper surface of the bit line to an uppermost portion of the gate insulating layer is greater than a height from the upper surface of the bit line to an uppermost portion of the first channel pattern. (the uppermost portion is defined in the diagram above to be below the uppermost portion of the gate insulating layer )
Regarding Claim 11 Ryu teaches
A semiconductor memory device (Fig 1-10)comprising:
a peripheral gate structure (PT including layers 220, 230, and 210 Para[0070]-[0074]) on a substrate (100);
a bit line (120 Para[0030]) on (above) the peripheral gate structure, wherein the bit line extends in a first direction(X);
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a protruded insulating pattern (inner portions of 112 and 116) on the bit line(120), and in a channel trench;
a channel structure (130) on the bit line(120), wherein the channel structure includes a horizontal portion and first (left) and second (right) vertical portions which are inside the channel trench, wherein the first and second vertical portions protrude from the horizontal portion, and wherein the horizontal portion of the channel structure is in contact with the bit line(fig 9b);
a channel interfacial layer (outer portions of 112, see diagram above)between the protruded insulating pattern and the channel structure;
a first word line (150a) on the channel structure, wherein the first word line extends in a second direction (Y) that intersects the first direction(X);
a second word line(150b) on the channel structure, wherein the second word line extends in the second direction (Y)and is spaced apart from the first word line(150a) in the first direction(X)(Fig 9b);
a gate isolation pattern(114) on the horizontal portion of the channel structure, wherein the gate isolation pattern separates the first word line(150a) and the second word line(150b) from each other(Fig 9b); and
a first capacitor (170a)and a second capacitor (170b)which are electrically connected to the first vertical portion(left) of the channel structure (130)and the second vertical portion(right) of the channel structure(130), respectively.(Fig 9b)
Regarding Claim 12 Ryu teaches
The semiconductor memory device of claim 11,
wherein the channel interfacial layer (outer portions of 112) includes at least one of a silicon oxide (Para [0035]), a silicon oxynitride, a silicon nitride or a metal oxide.
Regarding Claim 13 Ryu teaches
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The semiconductor memory device of claim 12, wherein the metal oxide is an insulating material. (This limitation has been considered because Ryu teaches a silicon oxide)
Regarding Claim 14 Ryu teaches
The semiconductor memory device of claim 11,
wherein a height from an upper surface of the bit line to an upper surface of the gate isolation pattern (114) is greater than a height from the upper surface of the bit line to an uppermost portion of the first vertical portion of the channel structure. (the uppermost portion is defined in the diagram above to be below the uppermost portion of the gate isolation pattern )
Regarding Claim 15 Ryu teaches
The semiconductor memory device of claim 11,
wherein the protruded insulating pattern (inner portions of 112 and including 116) includes a lower protruded insulating pattern (inner portions of 112) and an upper protruded insulating pattern(116), wherein the lower protruded insulating pattern is between the bit line (120 Fig 9b) and the upper protruded insulating pattern(116), wherein the lower protruded insulating pattern includes a silicon oxide(Para [0035] teaches that 112 maybe at least on of silicon oxide), and wherein the upper protruded insulating pattern (116) includes a silicon nitride. (Para [0120] teaches that 116 is a second interlayer insulating layer which is similar to the first interlayer insulating layer 112. And Para [0035] teaches silicon nitride would be an option of material for the first interlayer insulating layer 112. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form 116 out of a silicon nitride because it is a known material for interlayer insulating layers.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. MA; JINWON ( US-20220172749-A1), Park; Jung Min (US-20220238641-A1), JUNG; Hae Geon (US-20220344461-A1), JEONG; Jae Kyeong (US-20220367721-A1), Guo; Shuai (US-11508731-B1), Cho; Minhee (US-20220384661-A1), Lee; Jinho (US-20220416010-A1), LEE; Kyunghwan (US-20230307448-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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