DETAILED ACTION
This correspondence is in response to the communications received 02/09/2024. Claims 1-19 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/09/2024 and 03/30/2026 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a method of manufacturing a semiconductor device (100), comprising steps of:
(a) (Fig. 6) preparing a semiconductor substrate (SUB) of a first conductive type, the semiconductor substrate having an upper surface (TS) and a lower surface (BS);
(b) after the step of (a), (Fig. 7) forming a trench (TR) in the semiconductor substrate to have a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate;
(c) after the step of (b), (Fig. 8) forming a first insulating film (IF1) on the upper surface of the semiconductor substrate and in an inside of the trench;
(d) after the step of (c), (Fig. 8) forming a first conductive film (CF1) on the first insulating film so as to fill the inside of the trench;
(e) after the step of (d), (Fig. 9) forming, as a field plate electrode (FP), the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench;
(f) after the step of (e), (Fig. 10) selectively removing an another part of the field plate electrode such that a part of the field plate electrode is left as a lead portion (FPa);
(g) after the step of (f), (Fig. 11) removing the first insulating film located on the upper surface of the semiconductor substrate, and recessing the first insulating film located in the inside of the trench toward a bottom portion of the trench such that an upper surface of the first insulating film located in the inside of the trench is positioned lower than an upper surface of the field plate electrode in cross sectional view;
(h) after the step of (g), (Fig. 12) forming a first protective film (PF1) on the upper surface of the semiconductor substrate and in the inside of the trench so as to cover the field plate electrode and the first insulating film;
(i) after the step of (h), (Fig. 13) removing the first protective film located on the upper surface of the semiconductor substrate, and recessing the first protective film located in the inside of the trench toward the bottom portion of the trench such that an upper surface of the first protective film located in the inside of the trench is positioned lower than the upper surface of the field plate electrode in cross sectional view;
(j) after the step of (i), (Fig. 14) forming a gate insulating film (GI) in the inside of the trench, which is located at a portion over the first protective film, and forming a second insulating film (IF2) so as to cover the field plate electrode exposed from the first protective film;
(k) after the step of (j), (Fig. 14) forming a second conductive film (CF2) on each of the gate insulating film, the second insulating film and the first protective film so as to fill the inside of the trench; and
(l) after the step of (k), (Fig. 16) forming, as a gate electrode (GE), the second conductive film left in the inside of the trench, which is located at a portion over the field plate electrode, by removing the second conductive film located in the outside of the trench, wherein the second conductive film formed on the first protective film and the second insulating film, which are in contact with the lead portion, in the step of (k) is removed in the step of (l).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20230072989 A1, published 03/09/2023) in view of Osawa (US 10,192,962 B2, published 01/29/2019) in view of Cannon et al. (US 7,965,540 B2, published 06/21/2011) in view of Krishnan et al (US 20110298089 A1, published 12/08/2011).
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Regarding claim 1, Figs. 1-7 and 8A-8T of Nagata disclose a method of manufacturing a semiconductor device (“FIG. 8A to FIG. 8T are cross-sectional views for describing one example of a method for manufacturing the semiconductor device 1 shown in FIG. 1”, [0185]), comprising steps of:
(a) preparing a semiconductor substrate of a first conductive type (“The epitaxial wafer 81 has a laminated structure which includes an n+-type semiconductor wafer 84 and an n-type epitaxial layer 85. The epitaxial layer 85 is formed by epitaxial growth of silicon from a main surface of the semiconductor wafer 84”, [0187]), the semiconductor substrate having an upper surface (“first wafer main surface 82”, [0186], as seen in Fig. 8A, 82 is an upper surface) and a lower surface (“second wafer main surface 83”, [0186], as seen in Fig. 8A, 83 is a lower surface);
(b) after the step of (a), forming a trench in the semiconductor substrate (“Next, with reference to FIG. 8B, a hard mask 86 having a predetermined pattern is formed on the first wafer main surface 82. The hard mask 86 exposes regions of the first wafer main surface 82 in which a plurality of first trenches 22, a plurality of second trenches 32, and a plurality of third trenches 42 are to be formed”, [0188]) to have a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate (as seen in Fig. 8B, 22, 32, and 42 are etched to a predetermined depth in which they do not extend into 84, further 22, 32, and 42, extend from 82 toward 83);
(c) after the step of (b), forming a first insulating film (“Next, with reference to FIG. 8C, a first base insulating film 87 is formed on the first wafer main surface 82. The first base insulating film 87 serves as a base of the first insulating film 23, the third insulating film 34, and the fifth insulating film 44.”, [0190]) on the upper surface of the semiconductor substrate and in an inside of the trench (as seen in Fig. 8C, 87 is formed on 82 and in an inside of 22, 32, and 42);
(d) after the step of (c), forming a first conductive film on the first insulating film (“Next, with reference to FIG. 8D, a first base electrode layer 88 is formed on the first base insulating film 87. The first base electrode layer 88 contains a conductive polysilicon and serves as a base of the first electrode 24, the third electrode 36, and the fifth electrode 46”, [0191]), so as to fill the inside of the trench (“The first base electrode layer 88 fills the plurality of first trenches 22, the plurality of second trenches 32, and the plurality of third trenches 42”, [0191]);
(e) after the step of (d), forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film (“Next, with reference to FIG. 8E, an unnecessary portion of the first base electrode layer 88 is removed by an etching method until the first base insulating film 87 is exposed”, [0192], Nagata does not specify that the remaining portion of 88 is a field plate electrode, however a secondary reference will be used to teach this reference below) located in an outside of the trench (as seen in Fig. 8E, 88 is removed in an outside of 22, 32, and 42).
Nagata fails to disclose “(e) after the step of (d), forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench”.
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However, in a similar field of endeavor, Figs. 1, 2, 4, and 5A-5J of Osawa teach (e) after the step of (d), forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench (“Next, with reference to FIG. 5D, unnecessary portions of the first conductor film 33 are removed, for example, by etching back. The field plate electrodes 7 are thereby formed by the first conductor film 33 embedded in the first trenches 6”, col. 10, lines 59-63, as 33 of Osawa is equivalent to 88 of Nagata, and 7 of Osawa is equivalent to 24, 36, and 46 of Nagata, 24, 36, and 46 of Nagata are also field plate electrodes).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “(e) after the step of (d), forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench” as taught by Osawa in the system of Nagata for the purpose of providing electrical contact to the interior of the trench capacitor.
Figs. 1-7 and 8A-8T of Nagata further disclose (f) after the step of (e), selectively removing an another part of the field plate electrode (“Next, an unnecessary portion of the first base electrode layer 88 is removed by an etching method via the resist mask 89”, [0193]) such that a part of the field plate electrode is left as a lead portion (as seen in Figs. 3-6 and 8F, portions of 88 in 32 and 42 become “lead-out electrodes 36A”, [0178], and “lead-out electrodes 46A”, [0163], respectively);
(g) after the step of (f), removing the first insulating film located on the upper surface of the semiconductor substrate (“Next, with reference to FIG. 8G, an unnecessary portion of the first base insulating film 87 is removed by an etching method via the resist mask 89. The etching method may be a wet etching method and/or a dry etching method. Thereby, the first insulating film 23, the third insulating film 34, and the fifth insulating film 44 are formed”, [0194]), and recessing the first insulating film located in the inside of the trench toward a bottom portion of the trench such that an upper surface of the first insulating film located in the inside of the trench is positioned lower than an upper surface of the field plate electrode in cross sectional view (as seen in Fig. 8G, 34 and 44, formerly 87, are recessed inside 32 and 42 such that an upper surface of 34 and 44 exposed from 89 is positioned lower than an upper surface of 88 in cross section view);
Nagata in combination with Osawa fails to disclose “(h) after the step of (g), forming a first protective film on the upper surface of the semiconductor substrate and in the inside of the trench so as to cover the field plate electrode and the first insulating film;
(i) after the step of (h), removing the first protective film located on the upper surface of the semiconductor substrate, and recessing the first protective film located in the inside of the trench toward the bottom portion of the trench such that an upper surface of the first protective film located in the inside of the trench is positioned lower than the upper surface of the field plate electrode in cross sectional view”.
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However, in a similar field of endeavor, Figs. 1-3 and 4(a)-4(k) of Cannon teach (h) after the step of (g), forming a first protective film (“oxide isolation collar 226 is formed, such as by conformal deposition of CVD oxide”, col. 5, lines 47-48, 226 will help protect the upper portions of the structure of Nagata from the charges present in the trench structure and is therefore a protective film) on the upper surface of the semiconductor substrate and in the inside of the trench so as to cover the field plate electrode and the first insulating film (one having ordinary skill in the art would understand that a conformal coating would include film deposition on every exposed surface thus covering both the upper surface of the semiconductor substrate and the inside of the trench including the field plate electrode and the first insulating film);
(i) after the step of (h), removing the first protective film located on the upper surface of the semiconductor substrate, and recessing the first protective film located in the inside of the trench toward the bottom portion of the trench (as seen in Fig. 4(c) and previously discussed, portions of 226 are removed from the upper surface of “bulk substrate 210”, col. 5, line 21, and recessed in “deep trench 202”, col. 5, lines 25-26, towards the bottom of 202) such that an upper surface of the first protective film located in the inside of the trench is positioned lower than the upper surface of the field plate electrode in cross sectional view (as seen in Fig. 4(d), the upper surface of 226 located in 202 is position lower than the upper surface of “polysilicon buried strap 230”, col. 5, line 62, which together with “N+ polysilicon material 224”, col. 5, line 39 is equivalent to 24, 36, and 46 of Nagata).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “(h) after the step of (g), forming a first protective film on the upper surface of the semiconductor substrate and in the inside of the trench so as to cover the field plate electrode and the first insulating film;
(i) after the step of (h), removing the first protective film located on the upper surface of the semiconductor substrate, and recessing the first protective film located in the inside of the trench toward the bottom portion of the trench such that an upper surface of the first protective film located in the inside of the trench is positioned lower than the upper surface of the field plate electrode in cross sectional view” as taught by Cannon in the system of Nagata in combination with Osawa for the purpose of suppressing undesired parasitic leakage (Krishnan, [0002]).
Figs. 1-7 and 8A-8T of Nagata further disclose (j) after the step of (i), forming a gate insulating film in the inside of the trench (“Next, with reference to FIG. 8J, a third base insulating film 91 is formed as a film along the first wafer main surface 82, the wall surfaces of the plurality of second trenches 32, and the wall surfaces of the plurality of third trenches 42. The third base insulating film 91 serves as a base of the second insulating film 33, the fourth insulating film 43, and the first main surface insulating film 51”, [0198], as seen in Fig. 8J, 91 is on 34 and 44, further as seen in Fig. 5, 51, a portion of 91, is present in “trench gate structures 31”, [0200] and “dummy trench gate structures 41”, [0200], thus portions of 91 are a gate insulating film), which is located at a portion over the first protective film, and forming a second insulating film (“Next, with reference to FIG. 8H, a second base insulating film 90 is formed on the first wafer main surface 82. The second base insulating film 90 contains a silicon oxide and serves as a base of the first intermediate insulating film 37 and the second intermediate insulating film 47. The second base insulating film 90 fills the plurality of second trenches 32 and the plurality of third trenches 42 and covers the first wafer main surface 82”, [0195]) so as to cover the field plate electrode exposed from the first protective film (as seen in Fig. 8I, 90/37/47 covers 36 and 46 which are exposed from 34 and 44 respectively);
(k) after the step of (j), forming a second conductive film on each of the gate insulating film, the second insulating film and the first protective film so as to fill the inside of the trench (“Next, with reference to FIG. 8K, a second base electrode layer 92 is formed on the third base insulating film 91. The second base electrode layer 92 contains a conductive polysilicon and serves as a base of the second electrode 35 and the fourth electrode 45. The second base electrode layer 92 fills the plurality of second trenches 32 and the plurality of third trenches 42 across the third base insulating film 91”, [0199], as seen in Fig. 8K, 92 is 37 and 47, further, after combining Nagata and 226 of Cannon, 92 of Nagata will be formed on 226 as 92 is deposited over the entirety of 1 of Nagata); and
(l) after the step of (k), forming, as a gate electrode, the second conductive film left in the inside of the trench, which is located at a portion over the field plate electrode, by removing the second conductive film located in the outside of the trench (“Next, with reference to FIG. 8L, an unnecessary portion of the second base electrode layer 92 is removed by an etching method until the first main surface insulating film 51 is exposed. The etching method may be a wet etching method and/or a dry etching method. Thereby, the second electrode 35 and the fourth electrode 45 are formed. Further, the plurality of field trench structures 21, the plurality of trench gate structures 31, and the plurality of dummy trench gate structures 41 are formed”, [0200], and as seen in Fig. 5, 35 is part of 31, thus 35 is a gate electrode, further as seen in Fig. 8L, 35 is in 32, and located at a portion over 34),
wherein the second conductive film formed on the first protective film and the second insulating film, which are in contact with the lead portion, in the step of (k) is removed in the step of (l) (as seen in Figs. 6 and 8L, the remaining portion of 92/35/45 is only present in 22, 32, and 42 where 36A and 46A are not present, thus it must have necessarily been removed from 37 and 47 in contact with 36A and 46A, and would have been removed from 226 of Cannon in contact with 36A and 46A after combination of Nagata and Cannon).
Regarding claim 4, Figs. 1-7 and 8A-8T of Nagata in combination with Figs. 1, 2, 4, and 5A-5J of Osawa, Figs. 1-3 and 4(a)-4(k) of Cannon, and Krishnan disclose the method of manufacturing the semiconductor device according to claim 1, Figs. 1-7 and 8A-8T of Nagata further disclose further comprising steps of:
(m) after the step of (1), forming a third insulating film on the upper surface of the semiconductor substrate and on the gate electrode (“Next, with reference to FIG. 8N, a second main surface insulating film 52 is formed on the first main surface insulating film 51. The second main surface insulating film 52 collectively covers the plurality of field trench structures 21, the plurality of trench gate structures 31, and the plurality of dummy trench gate structures 41”, [0203], as seen in Fig. 8N, 52 is on 82, 35, and 45); and
(n) after the step of (m), removing the third insulating film and the gate insulating film in the outside of the trench (“Next, an unnecessary portion of the main surface insulating film 50 is removed by an etching method via the resist mask 93”, [0205], as seen in Fig. 8O, 50 includes 52, and portions of 52 outside of 22, 32, and 42 are removed).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20230072989 A1, published 03/09/2023) in view of Osawa (US 10,192,962 B2, published 01/29/2019) in view of Cannon et al. (US 7,965,540 B2, published 06/21/2011) in view of Krishnan et al (US 20110298089 A1, published 12/08/2011) in view of Lee et al. (US 7,419,872 B2, published 09/02/2008) in view of Makala et al. (US 11,387,244 B2, published 07/12/2022).
Regarding claim 2, Figs. 1-7 and 8A-8T of Nagata in combination with Figs. 1, 2, 4, and 5A-5J of Osawa, Figs. 1-3 and 4(a)-4(k) of Cannon, and Krishnan disclose the method of manufacturing the semiconductor device according to claim 1, Figs. 1-7 and 8A-8T of Nagata further disclose wherein each of the first insulating film and the first protective film is a silicon oxide film (Nagata states “The epitaxial layer 85 is formed by epitaxial growth of silicon”, [0187], and “The first base insulating film 87 may be formed by a CVD method and/or an oxidation treatment method (for example, thermal oxidation treatment method)”, [0190], one having ordinary skill in the art would understand that thermal oxidation of the silicon of 85 would produce silicon oxide, further, “The second base insulating film 90 contains a silicon oxide”, [0195], and as seen in Fig. 8H, 90 is made of the same material as 34/44 which were formerly 87, neither Nagata nor Cannon disclose that 226 is made of silicon oxide, however a secondary reference will be used to teach this limitation below)
Nagata in combination with Osawa, Cannon and Krishna fail to disclose “wherein each of the first insulating film and the first protective film is a silicon oxide film, and
the step of (g) and the step of (i) are performed by an isotropic etching process using solution containing hydrofluoric acid.”
However, in a similar field of endeavor, Figs. 1-16 of Lee teach wherein each of the first insulating film and the first protective film is a silicon oxide film (“Referring to FIG. 10, a deposition process is performed to form a collar insulation layer 34 on the upper inner sidewall of the trench 18, i.e., covering the dielectric layer 28 above the top electrode 30', wherein the collar insulation layer 34 can be formed of silicon oxide”, col. 3, lines 9-13, thus 226 of Cannon can be formed of silicon oxide).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein each of the first insulating film and the first protective film is a silicon oxide film” as taught by Lee in the system of Nagata in combination with Osawa, Cannon and Krishna for the purpose of providing a specific collar composition.
Nagata in combination with Osawa, Cannon, Krishna, and Lee fail to disclose “the step of (g) and the step of (i) are performed by an isotropic etching process using solution containing hydrofluoric acid.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5A-5P of Makala the step of (g) and the step of (i) are performed by an isotropic etching process using solution containing hydrofluoric acid (“An isotropic etch process that etches the material of the insulating layers 32 selective to the material of the spacer material layers can be performed to laterally recess the physically exposed sidewalls of the insulating layers 32 relative to sidewalls of the spacer material layers (such as the sacrificial material layers). In one embodiment, the physically exposed surfaces of the insulating cap layer 70 may be isotropically recessed concurrently with formation of the annular lateral recesses 149. In an illustrative example, the insulating layers 32 include silicon oxide, the spacer material layers 42 include silicon nitride or a semiconductor material (such as polysilicon), and the isotropic etch process comprises a wet etch process employing dilute hydrofluoric acid”, col. 14, lines 61-67 and col. 15, lines 1-8, thus hydrofluoric acid can be used to isotropically wet etch silicon oxide, this process can therefore be applied to the wet etch processes disclosed by Nagata used to remove the unnecessary portion of 87 of Nagata and 226 of Cannon).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the step of (g) and the step of (i) are performed by an isotropic etching process using solution containing hydrofluoric acid”” as taught by Makala in the system of Nagata in combination with Osawa, Cannon, Krishna, and Lee for the purpose of providing an etch chemistry for silicon oxide.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20230072989 A1, published 03/09/2023) in view of Osawa (US 10,192,962 B2, published 01/29/2019).
Regarding claim 13, Figs. 1-7 and 8A-8T of Nagata disclose a method of manufacturing a semiconductor device (“FIG. 8A to FIG. 8T are cross-sectional views for describing one example of a method for manufacturing the semiconductor device 1 shown in FIG. 1”, [0185]), comprising steps of:
(a) preparing a semiconductor substrate of a first conductive type (“The epitaxial wafer 81 has a laminated structure which includes an n+-type semiconductor wafer 84 and an n-type epitaxial layer 85. The epitaxial layer 85 is formed by epitaxial growth of silicon from a main surface of the semiconductor wafer 84”, [0187]), the semiconductor substrate having an upper surface (“first wafer main surface 82”, [0186], as seen in Fig. 8A, 82 is an upper surface) and a lower surface (“second wafer main surface 83”, [0186], as seen in Fig. 8A, 83 is a lower surface);
(b) after the step of (a), forming a trench in the semiconductor substrate (“Next, with reference to FIG. 8B, a hard mask 86 having a predetermined pattern is formed on the first wafer main surface 82. The hard mask 86 exposes regions of the first wafer main surface 82 in which a plurality of first trenches 22, a plurality of second trenches 32, and a plurality of third trenches 42 are to be formed”, [0188]) to have a predetermined depth from the upper surface of the semiconductor substrate (as seen in Fig. 8B, 22, 32, and 42 are etched to a predetermined depth in which they do not extend into 84);
(c) after the step of (b), forming a first insulating film (“Next, with reference to FIG. 8C, a first base insulating film 87 is formed on the first wafer main surface 82. The first base insulating film 87 serves as a base of the first insulating film 23, the third insulating film 34, and the fifth insulating film 44.”, [0190]) on the upper surface of the semiconductor substrate and in an inside of the trench (as seen in Fig. 8C, 87 is formed on 82 and in an inside of 22, 32, and 42);
(d) after the step of (c), forming a first conductive film on the first insulating film (“Next, with reference to FIG. 8D, a first base electrode layer 88 is formed on the first base insulating film 87. The first base electrode layer 88 contains a conductive polysilicon and serves as a base of the first electrode 24, the third electrode 36, and the fifth electrode 46”, [0191]), so as to fill the inside of the trench (“The first base electrode layer 88 fills the plurality of first trenches 22, the plurality of second trenches 32, and the plurality of third trenches 42”, [0191]);
(e) after the step of (d), forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film (“Next, with reference to FIG. 8E, an unnecessary portion of the first base electrode layer 88 is removed by an etching method until the first base insulating film 87 is exposed”, [0192], Nagata does not specify that the remaining portion of 88 is a field plate electrode, however a secondary reference will be used to teach this reference below) located in an outside of the trench (as seen in Fig. 8E, 88 is removed in an outside of 22, 32, and 42);
(f) after the step of (e), forming a mask layer, (“Next, with reference to FIG. 8F, a resist mask 89 having a predetermined pattern is formed on the first wafer main surface 82. The resist mask 89 covers the plurality of first trenches 22 and exposes the plurality of second trenches 32 and the plurality of third trenches 42. Next, an unnecessary portion of the first base electrode layer 88 is removed by an etching method via the resist mask 89 ... Thereby, the first electrode 24, the third electrode 36 and the fifth electrode 46 are formed”, [0193]) which has a pattern covering a part of the field plate electrode and exposing an another part of the field plate electrode, on the upper surface of the semiconductor substrate (as seen in Fig. 8F, 89 has a pattern covering a part of 88, and exposing an another part of 88 on 82);
(g) after the step of (f), selectively recessing the another part of the field plate electrode while using the mask layer as a mask (“Next, an unnecessary portion of the first base electrode layer 88 is removed by an etching method via the resist mask 89”, [0193]) such that the part of the field plate electrode is left as a lead portion (as seen in Figs. 3-6 and 8F, portions of 88 in 32 and 42 become “lead-out electrodes 36A”, [0178], and “lead-out electrodes 46A”, [0163], respectively); and
(h) after the step of (g), removing the first insulating film located on the upper surface of the semiconductor substrate exposed from the mask layer (“Next, with reference to FIG. 8G, an unnecessary portion of the first base insulating film 87 is removed by an etching method via the resist mask 89. The etching method may be a wet etching method and/or a dry etching method. Thereby, the first insulating film 23, the third insulating film 34, and the fifth insulating film 44 are formed”, [0194]), and recessing the first insulating film located in the inside of the trench such that an upper surface of the first insulating film exposed from the mask layer is positioned lower than an upper surface of the field plate electrode in cross sectional view while using the mask layer as a mask (as seen in Fig. 8G, 34 and 44, formerly 87, are recessed inside 32 and 42 such that an upper surface of 34 and 44 exposed from 89 is positioned lower than an upper surface of 88 in cross section view while using 89 as a mask).
Nagata fails to disclose “forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench”.
However, in a similar field of endeavor, Figs. 1, 2, 4, and 5A-5J of Osawa teach forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench (“Next, with reference to FIG. 5D, unnecessary portions of the first conductor film 33 are removed, for example, by etching back. The field plate electrodes 7 are thereby formed by the first conductor film 33 embedded in the first trenches 6”, col. 10, lines 59-63, as 33 of Osawa is equivalent to 88 of Nagata, and 7 of Osawa is equivalent to 24, 36, and 46 of Nagata, 24, 36, and 46 of Nagata are also field plate electrodes).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming, as a field plate electrode, the first conductive film left in the inside of the trench by removing the first conductive film located in an outside of the trench” as taught by Osawa in the system of Nagata for the purpose of providing electrical contact to the interior of the trench capacitor.
Regarding claim 14, Figs. 1-7 and 8A-8T of Nagata in combination with Figs. 1, 2, 4, and 5A-5J of Osawa disclose the method of manufacturing the semiconductor device according to claim 13, Figs. 1-7 and 8A-8T of Nagata further disclose further comprising steps of:
(i) after the step of (h), removing the mask layer (“an unnecessary portion of the first base insulating film 87 is removed by an etching method via the resist mask 89 … The resist mask 89 is thereafter removed”, [0194]);
(j) after the step of (i), forming a gate insulating film in the inside of the trench on the first insulating film (“Next, with reference to FIG. 8J, a third base insulating film 91 is formed as a film along the first wafer main surface 82, the wall surfaces of the plurality of second trenches 32, and the wall surfaces of the plurality of third trenches 42. The third base insulating film 91 serves as a base of the second insulating film 33, the fourth insulating film 43, and the first main surface insulating film 51”, [0198], as seen in Fig. 8J, 91 is on 34 and 44, further as seen in Fig. 5, 51, a portion of 91, is present in “trench gate structures 31”, [0200] and “dummy trench gate structures 41”, [0200], thus portions of 91 are a gate insulating film) and forming a second insulating film (“Next, with reference to FIG. 8H, a second base insulating film 90 is formed on the first wafer main surface 82. The second base insulating film 90 contains a silicon oxide and serves as a base of the first intermediate insulating film 37 and the second intermediate insulating film 47. The second base insulating film 90 fills the plurality of second trenches 32 and the plurality of third trenches 42 and covers the first wafer main surface 82”, [0195]) so as to cover the field plate electrode exposed from the first insulating film (as seen in Fig. 8I, 90/37/47 covers 36 and 46 which are exposed from 34 and 44 respectively);
(k) after the step of (j), forming a second conductive film on the gate insulating film, on the second insulating film, and on the first insulating film so as to fill the inside of the trench (“Next, with reference to FIG. 8K, a second base electrode layer 92 is formed on the third base insulating film 91. The second base electrode layer 92 contains a conductive polysilicon and serves as a base of the second electrode 35 and the fourth electrode 45. The second base electrode layer 92 fills the plurality of second trenches 32 and the plurality of third trenches 42 across the third base insulating film 91”, [0199], as seen in Fig. 8K, 92 is also on 37, 47, 34, and 44); and
(l) after the step of (k), forming, as a gate electrode, the second conductive film left in the inside of the trench, which is located at a portion over the field plate electrode, by removing the second conductive film located in the outside of the trench (“Next, with reference to FIG. 8L, an unnecessary portion of the second base electrode layer 92 is removed by an etching method until the first main surface insulating film 51 is exposed. The etching method may be a wet etching method and/or a dry etching method. Thereby, the second electrode 35 and the fourth electrode 45 are formed. Further, the plurality of field trench structures 21, the plurality of trench gate structures 31, and the plurality of dummy trench gate structures 41 are formed”, [0200], and as seen in Fig. 5, 35 is part of 31, thus 35 is a gate electrode, further as seen in Fig. 8L, 35 is in 32, and located at a portion over 34),
wherein the mask layer is a first resist pattern (89 is a first resist pattern as “resist mask 93”, [0204], is also disclosed), and
the second conductive film formed on the first insulating film and on the second insulating film (see above), which are in contact with the lead portion (as seen in Fig. 6, 34 and 44 are in contact with 36A and 46A respectively, further, 37 and 47 are interpreted as being in contact with 36A and 46A. This interpretation is based on the Figs. 5 and 6 which represent sequential cross-sections indicating that the transition between Figs. 5 and 6 would require a vertical portion of 36A and 46A to be in contact with 37 and 47 respectively), in the step of (k) is removed in the step of (l) (as seen in Figs. 8K and 8L, the portion of 92 on 82 is removed in the formation of 35).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nagata (US 20230072989 A1, published 03/09/2023) in view of Osawa (US 10,192,962 B2, published 01/29/2019) in view of Makala et al. (US 11,387,244 B2, published 07/12/2022).
Regarding claim 15, Figs. 1-7 and 8A-8T of Nagata in combination with Figs. 1, 2, 4, and 5A-5J of Osawa disclose the method of manufacturing the semiconductor device according to claim 14, Figs. 1-7 and 8A-8T of Nagata further disclose wherein the first insulating film is a silicon oxide film (Nagata states “The epitaxial layer 85 is formed by epitaxial growth of silicon”, [0187], and “The first base insulating film 87 may be formed by a CVD method and/or an oxidation treatment method (for example, thermal oxidation treatment method)”, [0190], one having ordinary skill in the art would understand that thermal oxidation of the silicon of 85 would produce silicon oxide, further, “The second base insulating film 90 contains a silicon oxide”, [0195], and as seen in Fig. 8H, 90 is made of the same material as 34/44 which were formerly 87).
Nagata in combination with Osawa fails to disclose “the step of (h) is performed by an isotropic etching process using solution containing hydrofluoric acid”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5A-5P of Makala teach the step of (h) is performed by an isotropic etching process using solution containing hydrofluoric acid (“An isotropic etch process that etches the material of the insulating layers 32 selective to the material of the spacer material layers can be performed to laterally recess the physically exposed sidewalls of the insulating layers 32 relative to sidewalls of the spacer material layers (such as the sacrificial material layers). In one embodiment, the physically exposed surfaces of the insulating cap layer 70 may be isotropically recessed concurrently with formation of the annular lateral recesses 149. In an illustrative example, the insulating layers 32 include silicon oxide, the spacer material layers 42 include silicon nitride or a semiconductor material (such as polysilicon), and the isotropic etch process comprises a wet etch process employing dilute hydrofluoric acid”, col. 14, lines 61-67 and col. 15, lines 1-8, thus hydrofluoric acid can be used to isotropically wet etch silicon oxide, this process can therefore be applied to the wet etch process disclosed by Nagata used to remove the unnecessary portion of 87).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the step of (h) is performed by an isotropic etching process using solution containing hydrofluoric acid” as taught by Makala in the system of Nagata in combination with Osawa for the purpose of providing an etch chemistry for silicon oxide.
Allowable Subject Matter
Claims 6-12 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the method of manufacturing a semiconductor device as recited in the claims of the instant application.
Regarding claim 6, the prior art of Nagata (US 20230072989 A1) in combination with Osawa (US 10,192,962 B2), Cannon et al. (US 7,965,540 B2), and Krishnan et al (US 20110298089 A1) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding the second protective film, the field plate electrode, and the anisotropic etching process e.g. “(f) after the step of (e), forming a second protective film so as to cover the field plate electrode and the first insulating film on the upper surface of the semiconductor substate;
(g) after the step of (f), forming a first resist pattern, which has a pattern covering a part of the field plate electrode and exposing an another part of the field plate electrode, on the second protective film;
(h) after the step of (g), removing the second protective film formed on the another part of the field plate electrode by performing an anisotropic etching process while using the first resist pattern as a mask;
(i) after the step of (h), selectively recessing the another part of the field plate electrode such that the part of the field plate electrode is left as a lead portion by performing an etching process while using the first resist pattern as a mask”.
Claims 7-12 are allowable by virtue of their dependence on claim 6.
Claims 3, 5, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the method of manufacturing a semiconductor device as recited in the claims of the instant application.
Regarding claim 3, the prior art of Nagata (US 20230072989 A1) in combination with Osawa (US 10,192,962 B2), Cannon et al. (US 7,965,540 B2), and Krishnan et al (US 20110298089 A1) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding the thickness of the first protective film relative to the thickness of the first insulating film on the upper surface of the semiconductor substrate e.g. “wherein a thickness of the first protective film formed on the upper surface of the semiconductor substrate in the step of (h) is smaller than a thickness of the first insulating film formed on the upper surface of the semiconductor substrate in the step of (c).”
Regarding claim 5, the prior art of Nagata (US 20230072989 A1) in combination with Osawa (US 10,192,962 B2), Cannon et al. (US 7,965,540 B2), and Krishnan et al (US 20110298089 A1) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding a resist pattern to etch the lead portion of the field plate electrode e.g. “(o) after the step of (l) and before the step of (m), forming a resist pattern which has a pattern selectively opening the lead portion in the field plate electrode, on the upper surface of the semiconductor substrate; and
(p) after the step of (o) and before the step of (m), performing an etching process while using the resist pattern as a mask under a condition making the gate insulating film, the second insulating film, and the first protective film difficult to be etched and making the second conductive film easy to be etched.”
Regarding claim 16, the prior art of Nagata (US 20230072989 A1) in combination with Osawa (US 10192962 B2) discloses a similar method of manufacturing a semiconductor device but fails to disclose the specific claims of the instant application regarding a second resist pattern to etch the lead portion of the field plate electrode e.g. “(m) after the step of (l), forming a second resist pattern which has a pattern selectively opening the lead portion in the field plate electrode, on the upper surface of the semiconductor substrate; and
(n) after the step of (m), performing an etching process while using the second resist pattern as a mask under a condition making the gate insulating film and the second insulating film difficult to be etched and making the second conductive film easy to be etched.”.
Regarding claim 17, the prior art of Nagata (US 20230072989 A1) in combination with Osawa (US 10,192,962 B2) discloses a similar method of manufacturing a semiconductor device but fails to disclose but fails to disclose the specific claims of the instant application regarding forming the second conductive layer and the mask layer e.g. “(j) after the step of (i), forming a second conductive film on the gate insulating film, on the second insulating film, on the first insulating film, and on the mask layer so as to fill the inside of the trench;
(k) after the step of (j), forming, as a gate electrode, the second conductive film left in the inside of the trench, which is located at a portion over the field plate electrode, by removing the second conductive film located in the outside of the trench; and
(l) after the step of (k), removing the mask layer, wherein the mask layer is an insulating film made of a material different from the first insulating film, the second insulating film, the gate insulating film, the first conductive film, and the second conductive film, and the second conductive film formed on the mask layer in contact with the lead portion in the step of (j) is removed in the step of (k).”
Claims 18 and 19 are allowable by virtue of their dependence on claim 17.
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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