Prosecution Insights
Last updated: October 04, 2026
Application No. 18/437,960

OPTICAL DEVICE AND METHOD OF MANUFACTURE

Final Rejection §102
Filed
Feb 09, 2024
Examiner
CAPUTO, LISA M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
38%
Grant Probability
At Risk
3-4
OA Rounds
0m
Est. Remaining
44%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
23 granted / 61 resolved
-30.3% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
19 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 61 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Amendment/Response Receipt is acknowledged of the amendment and arguments filed July 6, 2026. Response to Arguments Applicant's arguments filed July 6, 2026 have been fully considered but they are not persuasive. In response to applicant’s arguments on page 9 of the remarks, that Allman fails to disclose that waveguides 25a and 25b are spaced apart, examiner respectfully disagrees and submits that the waveguides 25a and 25b are interpreted as being spaced apart in Figure 1, even though they are optically connected by intervening portion vertical waveguide 22. The waveguides are spaced apart as there are elements between the waveguides as can be seen in Figure 1, such as dielectric layer 26b and the Allman reference specifically states that this dielectric material separates the horizontal waveguides from one another (see col 4, lines 20-43). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Allman et al (U.S. Patent No. 6,324,313). Regarding claim 1, Allman teaches a method of manufacturing an optical device, the method comprising: forming a first waveguide (Fig. 1, 25a and Col 4 Ln 21-42) in a first insulating layer (Fig. 1, 26a, 26b, 26c; Col 4 Ln 33-35) over a substrate (Fig. 1, 24), wherein the first waveguide comprises a first major portion (Fig. 1, horizontal portion of 30 and 40) and a first bent portion (Fig. 1, bent portion of 30 and 36) extending upwardly from the first major portion away from the substrate; and forming a second waveguide (Fig. 1, 25b) over the first waveguide, wherein the second waveguide comprises a second major portion (Fig. 1, horizontal portion of 30 and 40b) over the first insulating layer and a second bent portion (Fig. 1, bent portion of 30 and 38) extending downwardly from the second major portion and into the first insulating layer, wherein the first waveguide is spaced apart from the second waveguide (see Figure 1). The waveguides 25a and 25b are interpreted as being spaced apart as can be explained by Allman when it is taught that “a portion of an integrated circuit (IC) -like structure 20 incorporating an on-chip multiple layer vertically transitioning optical waveguide 22 is shown in FIGS. 1 and 2. The IC-like structure 20 may have functional electronic components (not shown) located in a substrate 24. The functional components may be electrically connected to each other by interconnect electrical conductors (not shown) located in layers above the substrate 24 and/or by a vertical waveguide 22 and horizontal waveguides 25a, 25b, 25c and 25d, for example. The horizontal waveguides 25a, 25b, etc., are formed as distinct, vertically-spaced and horizontally-extending layers 27 of optical interconnects in the IC-like structure 20. Dielectric material 26, formed in layers 26a, 26b, 26c, etc., separates the horizontal waveguides 25a, 25b, 25c and 25d from one another, separates the horizontal layers 27 of the waveguides from one another, and also separates the functional components of the substrate 24 from the waveguides 22, 25a, 25b, 25c and 25d. The vertical waveguide 22 connects to and extends vertically through the dielectric material 26 between the horizontal waveguides 25a and 25c of the lower horizontal layer 27 the horizontal waveguides 25b and 25d of the upper vertical horizontal layer 27” (see Figure 1, col 4, lines 20-43). Regarding claim 2, Allman teaches that the first bent portion (Fig. 1, 36) of the first waveguide overlaps the second bent portion (Fig. 1, 38) of the second waveguide in a vertical direction. Allowable Subject Matter Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-14 and 21-26 are allowed. The best prior art of record fails to specifically teach the enumerated steps within these method claims, for example the second waveguide and process steps in independent claim 8 and the implant process of independent claim 21 “after forming the first recess, performing a first implant process to implant a first implant species in the first end portion of the first waveguide, wherein the first implant process bends the first end portion to form a first bent portion of the first waveguide.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Feb 09, 2024
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §102
Jul 06, 2026
Response Filed
Sep 08, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
38%
Grant Probability
44%
With Interview (+5.8%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 61 resolved cases by this examiner. Grant probability derived from career allowance rate.

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