Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and claim 7 of copending Application No. 18/437906 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other as disclosed in the table below.
Instant Claim 1
Co-pending Application No. 18/437906 (Reference Application)
A semiconductor device, comprising:
a first electrode;
Claim 1, A semiconductor device, comprising: a first electrode;
a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type;
Claim 1, a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type;
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type;
Claim 1, a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type;
a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type;
Claim 1, a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type;
a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region;
Claim 1, a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region;
a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction crossing the first and second directions, the first direction being from the first electrode toward the second electrode, the second direction being perpendicular to the first direction, a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first and second electrode regions;
Claim 1, a third electrode including a first electrode region extending along a second direction perpendicular to a first direction, the first electrode region being arranged with the second semiconductor region in a third direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first direction and crossing the second direction, a second electrode region extending along the third direction, the second electrode region being arranged with the second semiconductor region in the second direction, and a third electrode region connecting the first electrode region and the second electrode region;
a first insulating part including
a first insulating region including
a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and
a second insulating portion located between the first semiconductor region and the first electrode region in the first direction;
Claim 1, a first insulating part including a first insulating region including a first insulating portion located between the second semiconductor region and the first electrode region in the third direction, and a second insulating portion located between the first semiconductor region and the first electrode region in the first direction,
a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and
a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction,
Claim 1, a second insulating region including a third insulating portion located between the second semiconductor region and the second electrode region in the second direction, and a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction,
and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including
a fifth insulating portion located between the second semiconductor region and the third electrode region in a fourth direction perpendicular to the first direction, the fourth direction crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction;
Claim 1, and a third insulating region connecting the first insulating region and the second insulating region, the third insulating region including a fifth insulating portion located between the second semiconductor region and the second electrode region in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second and third directions, and a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction;
a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions;
Claim 1, a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions;
a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions;
Claim 1, a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions,
a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type.
Claim 7, a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ichinoseki (US 20210083108 A1) in view of Ding (US 20150060936 A1).
Re: Independent Claim 1, Ichinoseki discloses a semiconductor device (100), comprising:
a first electrode (Fig. 2 and ¶¶ [0024] - [0025], drain electrode 11);
a first semiconductor region located on the first electrode, the first semiconductor region being of a first conductivity type (Fig. 2 and ¶¶ [0024] - [0025], drift region 1 (first semiconductor region) of n-type located on first electrode 11);
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a second conductivity type (Fig. 2 and ¶¶ [0024] - [0025], p-type base regions 2 provided on first semiconductor region 1);
a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the first conductivity type (Fig. 2 and ¶¶ [0024] - [0025], n-type base regions 3 provided on second semiconductor region 2);
a second electrode located on the third semiconductor region, the second electrode being electrically connected with the third semiconductor region (Fig. 2 and ¶ [0031], source electrode 13 (second electrode) located on and electrically connected to third region 3);
a third electrode (gate electrode 10) including
a first electrode region extending along a second direction perpendicular to a first direction (Fig. 2 and ¶ [0028], portion of third electrode 10 extending between adjacent FP electrodes 12 which extends in the second direction D2 perpendicular to first direction D1), the first electrode region being arranged with the second semiconductor region in a third direction crossing the first and second directions (the portion of gate electrode 10 is arranged with the second semiconductor region 2 in the third direction D3; D3 is crossing the first direction D1 and the second direction D2), the first direction being from the first electrode toward the second electrode (D1 is the direction from first electrode 11 towards second electrode 13), the second direction being perpendicular to the first direction (D2 is perpendicular to D1),
a second electrode region extending along the third direction (portion of gate electrode (third electrode) 10 extending in third direction D3), the second electrode region being arranged with the second semiconductor region in the second direction (the portion of gate electrode 10 extending in third direction D3 (second electrode region) is arranged with second semiconductor region 2 in direction D2), and
a third electrode region connecting the first and second electrode regions (connecting/intersecting portion of gate electrode 10 connecting the D2-extending and D3-extending gate portions corresponds to the claimed third electrode region);
a first insulating part (gate insulating layer 10a) including
a first insulating region (gate insulating layer 10a includes a portion disposed along the D2-extending portion of gate electrode 10. As discussed above, the D2-extending portion of gate electrode 10 corresponds to the claimed first electrode region. Therefore, the portion of gate insulating layer 10a associated with the D2-extending portion of gate electrode 10 corresponds to the claimed first insulating region) including
a first insulating portion located between the second semiconductor region and the first electrode region in the third direction (the sidewall portion of gate insulating layer 10a located between p-type base region 2 and D2-extending portion of gate electrode 10 in the third direction D3 corresponds to the claimed first insulating portion), and
a second insulating portion located between the first semiconductor region and the first electrode region in the first direction (the bottom/lower portion of gate insulating layer 10a located between first semiconductor region 1 and the D2-extending portion of gate electrode 10 in the first direction D1 corresponds to the claimed second insulating portion);
a second insulating region (gate insulating layer 10a includes a portion disposed along the D3-extending portion of gate electrode 10. As discussed above, the D3-extending portion of gate electrode 10 corresponds to the claimed second electrode region. Therefore, the portion of gate insulating layer 10a associated with the D3-extending portion of gate electrode 10 corresponds to the claimed second insulating region) including
a third insulating portion located between the second semiconductor region and the second electrode region in the second direction (sidewall portion of gate insulating layer 10a located between second semiconductor region 2 and D3-extending portion of gate electrode 10 in the second direction D2 corresponds to the claimed third insulating portion), and
a fourth insulating portion located between the first semiconductor region and the second electrode region in the first direction (bottom/lower portion of gate insulating layer 10a located between first semiconductor region 1 and the D3-extending portion of gate electrode 10 in the first direction D1 corresponds to the claimed fourth insulating portion), and
a third insulating region connecting the first insulating region and the second insulating region (gate insulating layer 10a is provided along the continuous gate electrode 10, including the gate portion where the D2-extending the D3-extending portions of gate electrode 10 meet or connect. This insulating portion at the connecting/intersection portion of gate electrode 10 corresponds to the claimed third insulating region),
the third insulating region including a fifth insulating portion located between the second semiconductor region and the third electrode region in a fourth direction perpendicular to the first direction, the fourth direction crossing the second and third directions (sidewall portion of gate insulating layer 10a located between second semiconductor region 2 and the connecting/intersection portion of gate electrode 10 in a direction crossing D2 and D3 corresponds to the claimed fifth insulating portion. The claimed fourth direction is the direction from the p-type base region 2 toward the connecting/intersection portion of gate electrode 10 in plan view, and the fourth direction is perpendicular to the vertical first direction D1 and crossing the second and third directions D2 and D3), and
a sixth insulating portion located between the first semiconductor region and the third electrode region in the first direction (the bottom/lower insulating portion of gate insulating layer 10a located between the first semiconductor region 1 and the connecting/intersection portion of gate electrode 10 corresponds to the claimed sixth insulating portion);
a fourth electrode arranged with the first semiconductor region and the third electrode in the second and third directions (Fig. 2, ¶ [0028], FP electrode 12 arranged with first semiconductor region 1 and gate electrode 10 in the second direction D2 and third direction D3);
a second insulating part located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode in the second and third directions (insulating layer 12a between FP electrode 12 and region 1, and insulating layer 12a between FP electrode 12 and gate electrode 10 in the second direction D2 and third direction D3).
Ichinoseki is silent regarding
a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type.
However, Ding teaches a fourth semiconductor region located under the sixth insulating portion, the fourth semiconductor region being of the second conductivity type (Ding teaches, in Figs. 2E-2 to 2F-1 and ¶ [0032], P-type dopant regions 130 formed below the bottom of trench 120 and beneath oxide layers 115/125. Ding explains that these P-type regions, function as RESURF regions that improve breakdown-voltage capability at the trench bottom).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ichinoseki by providing Ding’s P-type trench-bottom dopant region 130 beneath the bottom insulating portion of Ichinoseki’s gate insulating layer 10a, including beneath the gate connection/intersection portion in order to increase breakdown-voltage blocking capability.
Re: Claim 2, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Ding further teaches
wherein the fourth semiconductor region includes: a first semiconductor portion overlapping the third electrode in the first direction (Ding teaches, in Fig. 2F-1, trench-bottom P-type dopant region 130 disposed below the bottom surface of trench 120. When Ding’s trench-bottom P-type dopant region 130 is applied under the bottom insulating portion of Ichinoseki’s gate electrode 10, the portion of P-type dopant region 130 located directly below gate electrode 10 overlaps the gate electrode 10 in the vertical first direction D1. This portion corresponds to the claimed first semiconductor portion overlapping the third electrode in the first direction); and a second semiconductor portion not overlapping the third electrode in the first direction (Ding teaches, in Fig. 2F-1 and ¶ [, sidewall/endpoint P-type dopant region 140 formed along trench endpoint sidewall 110 extending to reach the trench-bottom P-type dopant region 130. The sidewall/endpoint P-type dopant region 140 is laterally outside the vertical projection of the gate electrode and therefore does not overlap the gate electrode in the first direction D1. This portion corresponds to the claimed second semiconductor portion not overlapping the third electrode in the first direction).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include both the trench bottom P-type dopant region 130 and the connected sidewall/endpoint P-type dopant region 140 in the modified Ichinoseki device because Ding teaches that the sidewall/endpoint P-type dopant region 140 connects the trench-bottom P-type dopant region 130 to the P-type body region, thereby providing an effective PCOMP/RESURF structure for breakdown-voltage blocking capability.
Re: Claim 3, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Ding further teaches
wherein the fourth semiconductor region includes: a third semiconductor portion contacting the third insulating region (As discussed with respect to claim 1, Ichinoseki’s third insulating region corresponds to the portion of gate insulating layer 10a associated with the connecting/intersection portion of gate electrode 10. Ding teaches, in Fig. 2F-1, a sidewall/endpoint P-type dopant region 140 formed along a trench endpoint sidewall. When Ding’s P-type dopant structure is applied to Ichinoseki’s gate connection/intersection region, the sidewall/endpoint P-type dopant region 140 contacts the sidewall insulating portion of the gate insulating layer 10a associated with the connecting/intersection portion of gate electrode 10. This sidewall/endpoint P-type dopant region 140 corresponds to the claimed third semiconductor portion contacting the third insulating region); and
a fourth semiconductor portion located under the third semiconductor portion (Ding teaches, in Fig. 2F-1, a trench-bottom P-type dopant region 130 disposed below the bottom surface of the trench and connected to the sidewall/endpoint P-type dopant region 140. When applied to Ichinoseki, this trench-bottom P-type dopant region 130 is located below the sidewall/endpoint P-type dopant region 140. Therefore, Ding’s trench-bottom P-type dopant region 130 corresponds to the claimed fourth semiconductor portion located under the third semiconductor portion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Ding’s connected sidewall/endpoint P-type dopant region 140 and trench-bottom P-type dopant region 130 in the modified Ichinoseki device because Ding teaches that this connected P-type dopant structure links the P-type body region to the trench-bottom P-type dopant region and provides RESURF/breakdown-voltage blocking capability.
Re: Claim 4, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Ding further teaches
wherein the fourth semiconductor region includes: a fifth semiconductor portion overlapping the third electrode in the fourth direction; and a sixth semiconductor portion not overlapping the third electrode in the fourth direction (Ding teaches, in Fig. 2F-1, that the fourth semiconductor region includes multiple P-type portions, including trench-bottom P-type dopant region 130 and sidewall/endpoint P-type dopant region 140 connected to the trench-bottom P-type dopant region 130. The claimed fourth direction is an in-plane direction crossing the second and third directions. When Ding’s P-type dopant structure is applied to Ichinoseki’s gate connecting/intersecting region, the portion of trench-bottom P-type dopant region 130 aligned with the connecting/intersection portion of gate electrode 10 overlaps the third electrode region in the fourth direction and corresponds to the claimed fifth semiconductor portion. The laterally offset sidewall/endpoint P-type dopant region 140 does not overlap the third electrode region in the fourth direction and corresponds to the claimed sixth semiconductor portion).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Ding’s connected P-type dopant regions 130 and 140 in Ichinoseki to achieve PCOM structural configuration and provide RESURF/improve breakdown voltage blocking capability as taught by Ding.
Re: Claim 5, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Ichinoseki in view of Ding further teaches
wherein a lower end of the fourth semiconductor region is positioned higher than a lower end of the fourth electrode (Ichinoseki teaches FP electrode 12, corresponding to the claimed fourth electrode, formed in openings OP. Ichinoseki also teaches, in Figs. 7A-7B, gate electrode 10 formed in trench TR, where trench TR is shallower than openings OP. Thus, the lower end of FP electrode 12 is positioned deeper/lower than the bottom of the gate trench TR. Ding teaches P-type dopant region 130 formed below the bottom surface of a trench. When Ding’s P-type dopant region 130 is applied under the bottom insulating portion of Ichinoseki’s shallower gate trench TR, the lower end of the P-type dopant region 130 is positioned near the bottom of the shallower gate trench and higher than the lower end of the deeper FP electrode 12. Therefore, the lower end of the fourth semiconductor region is positioned higher than the lower end of the fourth electrode, as claimed).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Ding’s P-type dopant region 130 under Ichinoseki’s shallower gate trench TR while maintaining the P-type region above the lower end of FP electrode 12 in order to provide RESURF/electric-filed relaxation at the gate trench bottom without interfering the deeper electrode structure.
Re: Claim 7, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Ichinosek futher teaches
further comprising: a first connection part located between the third insulating region and the second insulating part in the second and third directions (As discussed in respect to claim 1 above, the third insulating region corresponds to the portion of gate insulating layer 10a associated with the connecting/intersection portion of gate electrode 10, and the second insulating part corresponds to insulating layer 12a/insulating portion 20 around FP electrode 12. In Fig. 2 and ¶ [0029] Ichinoseki’s p+-type contact regions 5 provided on p-type base region 2 in the repeated D2/D3 layout, and is located in the region between gate electrode 10/gate insulating layer 10a and FP electrode 12/insulating layer 12a in the repeated D2/D3 layout. Therefore, this contact portion 5 corresponds to the claimed first connection part located between the third insulating region and the second insulating part in the second and third directions ), the first connection part electrically connecting the second electrode and the second semiconductor region (Ichinoseki teaches, in ¶ [0031], source electrode 13 corresponds to the claimed second electrode, p-type base region 2 corresponds to the claimed second semiconductor region, and p-type base region 2 is electrically connected to source electrode 13 through p+-type contact region 5); and a second connection part located between the third insulating region and the first connection part in the fourth direction (Ichinosek teaches multiple p+-type contact regions 5 and connector/source-body contact portions in the repeated gate-electrode and FP-electrode layout. The fourth direction is an in-plane direction crossing the second and third directions. In Ichinosek’s repeated plan view layout, an additional contact portion 5 is located between the gate connecting/intersection insulating portion and the first contact portion in such an in-plane direction. Therefore, this additional contact portion corresponds to the claimed second connection part) , the second connection part electrically connecting the second electrode and the second semiconductor region (Ichinosek teaches the additional contact region 5 also electrically connect base region 2 to source electrode 13, as the same reason explained above).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichinoseki (US 20210083108 A1) in view of Ding (US 20150060936 A1) further in view of Hsieh (US 20120261737 A1).
Re: Claim 6, Ichinoseki and Ding disclose all the limitations of claim 1 on which this claim depends.
Both Ichinoseki and Ding are silent regarding
wherein a lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion
However, Hsieh teaches
wherein a lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion (Hsieh teaches trench MOSFET including first type trenched gates 210 in the active area and a second type trench gate 212 for gate connection. The first type trench gates 210 and second type trench gate 212 are each filled with a doped poly-silicon layer padded by gate oxide layer 208. Hsieh further teaches that the second type trenched gate 212 has a greater trench width and greater trench depth than the first type trench gates 210 and extends to the first type trenched gate 210. Therefore, the gate oxide layer 208 at the bottom of the deeper second type trench gate 212 is positioned lower than the gate oxide layer 208 at the bottom of the first type trenched gates 210).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ichinoseki so that the connection/intersection portion of gate electrode 10 is formed deeper than the D2-extending and D3-extending portions of gate electrode 10, as taught by the deeper gate-connection trench 212 of Hsieh, in order to provide a robust gate-connection structure and facilitate reliable electrical connection between gate portions. In the modified device, the bottom portion of gate insulating layer 10a under the deeper connection/intersection portion of gate electrode 10, corresponds to the claimed sixth insulating portion, has a lower end positioned lower than the lower ends of the bottom portions of gate insulating layer 10a under the D2-extending and D3-extending gate portions, corresponding to the claimed second and fourth portions.
Conclusion
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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