DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/13/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title includes the phrase “including test pads and heat dissipation structures”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5, the limitation "the plurality of lower bonding pads" in Lines L1-2, renders the claim indefinite because the antecedent basis is unclear as to whether “the plurality of lower bonding pads” (Lines L1-2) refers to a new plurality of lower bonding pads or the “lower bonding pad” previously cited in claim 4 Line L3. In the purpose of compact prosecution, “the plurality of lower bonding pads” has been interpretated as the lower bonding pad.
Regarding claim 9, the limitation "each conductive pads" in Line L2, renders the claim indefinite because the antecedent basis is unclear as to whether “each conductive pads” (Line L2) refers to a new conductive pads or the “plurality of conductive pads” previously cited in claim 1 Line L8. In the purpose of compact prosecution, “each conductive pads” has been interpretated as each of the plurality of conductive pads.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US20210156904A1 from IDS-Lim04).
Regarding claim 1, Lim04 discloses a high bandwidth memory structure (High bandwidth memory structure 10/100 -Examiner's annotated Fig 1, [0022] L1-4), comprising:
a buffer die comprising a plurality of conductive lines (Buffer die 300 comprising a plurality of conductive lines-Examiner's annotated Fig 1);
a memory stacking structure on the buffer die (Memory staking structure 100 on Buffer die 300-Examiner's annotated Fig 1),
wherein the memory stacking structure comprises
a plurality of memory dies that are stacked (Memory staking structure 100/200 on Buffer die 300, comprising a plurality of vertically stacked memory dies 130/140/150/160-Examiner's annotated Fig 1);
an interconnection structure between the buffer die and the memory stacking structure (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100/200-Examiner's annotated Fig 1),
wherein the interconnection structure comprises
a plurality of connection members (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100, comprising Connection members 122/110/320 surrounded by Insulating member 123-Examiner's annotated Fig 1) and
an insulating member surrounding the plurality of connection members (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100, comprising Connection members 122/110/320 surrounded by Insulating member 123-Examiner's annotated Fig 1); and
a plurality of conductive pads disposed on the buffer die and side by side with the plurality of connection members (Conductive pads 210/320/310 on Buffer die 300, side by side with Connection members 122/110/320-Examiner's annotated Fig 1),
wherein each conductive line of the plurality of conductive lines connects a connection member of the plurality of connection members to a conductive pad of the plurality of conductive pads ( Each of conductive lines connecting connection members 122/110/320 to conductive pads 210/320-Examiner's annotated Fig 1).
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Regarding claim 2, Lim04 discloses all the elements of claim 1.
Lim04 further discloses a high bandwidth memory structure
wherein the plurality of conductive pads include a test pad (Conductive pads 210/320/310 including test pad 310-Fig 2, [0044]).
Regarding claim 3, Lim04 discloses all the elements of claim 1.
Lim04 further discloses a high bandwidth memory structure
wherein the plurality of conductive pads are electrically insulated (Conductive pads 210/320/310 on substrate 340 so electrically insulated-Fig 2, [0039]).
Regarding claim 4, Lim04 discloses all the elements of claim 1.
Lim04 further discloses a high bandwidth memory structure
wherein each connection member among the plurality of connection members (Connection members 122/110/320-Examiner's annotated Fig 1) comprises:
a lower bonding pad (Connection members 122/110/320 comprising lower bonding pad 320-Examiner's annotated Fig 1); and
an upper bonding pad on the lower bonding pad (Connection members 122/110/320 comprising upper bonding pads 110 on lower bonding pads 320-Examiner's annotated Fig 1),
wherein the upper bonding pad is directly bonded to the lower bonding pad (upper bonding pads 110 directly bonded to lower bonding pads 320-Examiner's annotated Fig 1).
Regarding claim 5, Lim04 discloses all the elements of claim 4.
Lim04 further discloses a high bandwidth memory structure
wherein the plurality of conductive pads are disposed at the same level as the plurality of lower bonding pads (Conductive pads 210/320/310 at the same level as lower bonding pads 320 as indicated by the horizontal arrow-Examiner's annotated Fig 1).
Regarding claim 7, Lim04 discloses all the elements of claim 1.
Lim04 further discloses a high bandwidth memory structure
wherein the plurality of connection members include a micro-bump ( Connection members 122/110/320 comprising micro-bumps 110-Examiner's annotated Fig 1, [0022] L 1-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US20210156904A1 from IDS-Lim04) in view of Hung et al. (US 20240038718 A1-Hung18).
Regarding claim 6, Lim04 discloses all the elements of claim 4.
Lim04 does not disclose a high bandwidth memory structure
wherein the insulating member comprises:
a lower silicon insulating layer surrounding side surfaces of the plurality of lower bonding pads; and
an upper silicon insulating layer surrounding side surfaces of the plurality of upper bonding pads,
wherein the upper silicon insulating layer is directly bonded to the lower silicon insulating layer.
Hung18 teaches a high bandwidth memory structure
wherein the insulating member (insulating layer comprises:
a lower silicon insulating layer surrounding side surfaces of the plurality of lower bonding pads (Insulating member 124/224 comprising lower silicon insulating layer 224 surrounding side surface of lower bonding pad 128 and upper silicon insulating layer 124 surrounding side surface of upper bonding pad 128-[0020] L1-3, Examiner's annotated Fig 4); and
an upper silicon insulating layer surrounding side surfaces of the plurality of upper bonding pads (Insulating member 124/224 comprising lower silicon insulating layer 224 surrounding side surface of lower bonding pad 128 and upper silicon insulating layer 124 surrounding side surface of upper bonding pad 128-[0020] L1-3, Examiner's annotated Fig 4),
wherein the upper silicon insulating layer is directly bonded to the lower silicon insulating layer ( Upper silicon insulating layer 124 directly bonded to Lower silicon insulating layer 224-[0025] L1-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Hung18 for the purpose of allowing for packages to be manufactured with reduced process cost, reduced process steps, or reduced process time (Hung18: [0014]).
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Regarding claim 9, Lim04 discloses all the elements of claim 1.
Lim04 does not disclose a high bandwidth memory structure
wherein the insulating member surrounds a side surface of each conductive pads.
Hung18 teaches a high bandwidth memory structure
wherein the insulating member surrounds a side surface of each conductive pads (Insulating member 124/224 surrounding side surfaces of each conductive pads 128-[0020] L1-3, Examiner's annotated Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Hung18 for the purpose of allowing for packages to be manufactured with reduced process cost, reduced process steps, or reduced process time (Hung18: [0014]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US20210156904A1 from IDS-Lim04) in view of Oh et al. (US20140014958A1 from IDS-Oh58).
Regarding claim 8, Lim04 discloses all the elements of claim 1.
Lim04 does not disclose a high bandwidth memory structure
wherein the insulating member includes a non-conductive film (NCF).
Oh58 teaches a high bandwidth memory structure
wherein the insulating member includes a non-conductive film (NCF) (insulating member 300 includes a non-conductive film (NCF)-Fig 1, [0048] L3-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Oh58 for the purpose of attaching the chips to each other (Oh58: [0047]).
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US20210156904A1 from IDS-Lim04) in view of Kim et al. (US 20220013475 A1-Kim75).
Regarding claim 10, Lim04 discloses a high bandwidth memory structure (High bandwidth memory structure 10/100 -Examiner's annotated Fig 1, [0022] L1-4), comprising:
a buffer die comprising a plurality of conductive lines (Buffer die 300 comprising a plurality of conductive lines-Examiner's annotated Fig 1);
a memory stacking structure on the buffer die (Memory staking structure 100/200 on Buffer die 300-Examiner's annotated Fig 1),
wherein the memory stacking structure comprises
a plurality of memory dies that are stacked (Memory staking structure 100/200 on Buffer die 300, comprising a plurality of vertically stacked memory dies 130/140/150/160-Examiner's annotated Fig 1);
an interconnection structure between the buffer die and the memory stacking structure (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100-Examiner's annotated Fig 1),
wherein the interconnection structure comprises
a plurality of connection members (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100, comprising Connection members 122/110/320 surrounded by Insulating member 123-Examiner's annotated Fig 1) and
an insulating member surrounding the plurality of connection members (Interconnection structure 120 between Buffer die 300 and Memory stacking structure 100, comprising Connection members 122/110/320 surrounded by Insulating member 123-Examiner's annotated Fig 1); and
a plurality of conductive pads disposed on the buffer die and side by side with the plurality of connection members (Conductive pads 210/320/310 on Buffer die 300, side by side with Connection members 122/110/320-Examiner's annotated Fig 1),
wherein each conductive line of the plurality of conductive lines connects a connection member of the plurality of connection members to a conductive pad of the plurality of conductive pads ( Each of conductive lines connecting connection members 122/110/320 to conductive pads 210/320-Examiner's annotated Fig 1).
Lim04 does not disclose a high bandwidth memory structure comprising:
one or more heat dissipation structures disposed on the buffer die and disposed side by side with the memory stacking structure; and
a molding material disposed on the buffer die and molding the memory stacking structure and the one or more heat dissipation structures.
Kim75 teaches a high bandwidth memory structure comprising:
one or more heat dissipation structures disposed on the buffer die and disposed side by side with the memory stacking structure (One or more dissipation structure 140 disposed on buffer die 110 and disposed side by side with Memory stacking structure 120b-[0062] L1-14, Examiner's annotated Fig 13); and
a molding material disposed on the buffer die and molding the memory stacking structure and the one or more heat dissipation structures (Molding material 130 disposed on buffer die 110 and molding Memory stacking structure 120b and one or more dissipation structure 140-Examiner's annotated Fig 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Kim75 for the purpose of providing a semiconductor package with improved (e.g., reduced) warpage at room temperature and high temperature (Kim75:[0067]).
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Regarding claim 11, Lim04 and Kim75 combination discloses all the elements of claim 10.
Kim75 further teaches a high bandwidth memory structure
wherein the one or more heat dissipation structures are disposed on the plurality of conductive pads (One or more dissipation structure 140 disposed on conductive pads 13b-Examiner's annotated Fig 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Kim75 for the purpose of providing a semiconductor package with improved (e.g., reduced) warpage at room temperature and high temperature (Kim75:[0067]).
Regarding claim 12, Lim04 and Kim75 combination discloses all the elements of claim 10.
Lim04 further discloses a high bandwidth memory structure
wherein heat in the memory stacking structure is transferred through the plurality of conductive lines, the plurality of conductive pads (Conductive lines 330/350 and conductive pads 320/310/210 with 210 being microbumps 110 of Memory staking structure 100/200, are in metal material ([0025], [0044]-[0046]) as evidence by the electrical path along Conductive lines 330/350 and Conductive pads 320/310/210, therefore heat transferred through Conductive lines 330/350 and Conductive pads 320/310/210-Examiner’s annotated Fig 1).
Lim04 does not further disclose a high bandwidth memory structure
wherein heat in the memory stacking structure is transferred through the one or more heat dissipation structures.
Kim75 further teaches a high bandwidth memory structure
wherein heat in the memory stacking structure is transferred through the one or more heat dissipation structures (one or more heat dissipation structures heat sink 140 is/are in metal material ([0048]). Metals are good thermal conductor, therefore heat transferred through one or more heat dissipation structures 140-[0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Kim75 for the purpose of providing a semiconductor package with improved (e.g., reduced) warpage at room temperature and high temperature (Kim75:[0067]).
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Regarding claim 13, Lim04 and Kim75 combination discloses all the elements of claim 10.
Kim75 further teaches a high bandwidth memory structure
wherein the one or more heat dissipation structures includes a heat slug (one or more heat dissipation structures 140 includes a heat sink 140 so a heat slug as defined in paragraph [61] of application's specification-[0062] L2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Kim75 for the purpose of providing a semiconductor package with improved (e.g., reduced) warpage at room temperature and high temperature (Kim75:[0067]).
Regarding claim 14, Lim04 and Kim75 combination discloses all the elements of claim 13.
Kim75 further teaches a high bandwidth memory structure further comprising
a thermal interface material (TIM) between the buffer die and the heat slug (Thermal interface material (TIM) 42 disposed between buffer die 110 and heat slug 140-Examiner's annotated Fig 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Lim04, as taught by Kim75 for the purpose of providing a semiconductor package with improved (e.g., reduced) warpage at room temperature and high temperature (Kim75:[0067]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 20240395650 A1-Kim50) teaches a high bandwidth memory structure comprising one or more heat dissipation structures (180-Fig 1) disposed on the buffer die (180 disposed on 110-Fig 1) and disposed side by side with the memory stacking structure; (180 disposed side by side with 111-Fig 1) and
a molding material disposed on the buffer die (190 disposed on 110-Fig 1) and molding the memory stacking structure and the one or more heat dissipation structures (Fig 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 08/13/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights