DETAILED ACTION
This action is responsive to the following communication: the response filed 5/22/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-16, 18-21 pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/22/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ahn et al. (US 2024/0069790 “Ahn”).
Regarding claim 1, Ahn discloses an operation method of a memory system, comprising:
determining (fig. 16) that a memory device (200; fig. 1) of the memory system (fig. 1) is currently in a first use state (a first degradation state, having “a degradation parameter value [i.e. use state] corresponding to a selected memory block may be identified in operation S1300” para 0147) in response to determining (S120; fig. 12) that a read error is occurred (a read error occurred in a first read operation; para 0118) in the memory device (the memory device is determined to be in the first degradation state (YES S1310) as part of a second read operation S130, which is performed in response to determining the read error S120; fig. 12, 13, 16);
determining a first voltage offset (an offset voltage level may be selected from offset table S1330; fig. 16, detailed offset table β; fig. 14B, para 0129) corresponding to the first use state (S1330 corresponding to the first degradation state; fig. 16) according to a preset mapping relationship (fig. 15),
wherein the preset mapping relationship comprises corresponding relationships (para 0130) between different use states (different degradation states, i.e. the first degradation state having the degradation parameter value in RANGE 1, a different degradation state having another degradation parameter value in RANGE 2; fig. 15) of the memory device and respective voltage offsets (RANGE 1 in relation to offset β1, RANGE 2 in relation to offset β2; fig. 15), and the first voltage offset (i.e. the offset voltage level) comprises a first offset value (any offset value among values corresponding to R1-RN with respect to read voltages RP1-RP7; fig. 14B) relative to a preset reference read voltage (i.e. default read voltage), wherein each of the different use states (i.e. each degradation state) is based on a respective set of state parameters (degradation parameter(s), i.e. for accessing the memory in program, erase, read operations; para 0147) associated with one or more operations of the memory device (para 0046), and wherein the state parameters of the memory device comprise at least one of an erase count, a program count (P/E count; para 0142), a read count, a read temperature, a program temperature, or a program to read time interval of the memory device (i.e. “degradation parameter may include at least one selected from the group consisting of the number of error bits in data read based on an optimal read voltage set, temperature of a non-volatile memory, and a read count of the non-volatile memory” para 0145); and
obtaining at least one first read voltage (S134; fig. 13) for performing a read operation on the memory device (S135; fig. 13) in the first use state according to the preset reference read voltage and the first voltage offset (para 0119).
Regarding claim 11, Ahn discloses a memory controller coupled with one or more memory devices (1320a; fig. 21, further detailed 200; fig. 2), comprising:
at least one processor (1100; fig. 21); and
at least one memory storing programming instructions for executions by the at least one processor (para 0181-0183) to perform operations comprising:
in response to determining (S120; fig. 12) that a read error is occurred (a read error occurred in a first read operation; para 0118) in a memory device (200), determining that the memory device is in a first use state (a first degradation state having “a degradation parameter value [i.e. use state] corresponding to a selected memory block may be identified in operation S1300” para 0147; the memory device is determined to be in the first degradation state (YES S1310) as part of a second read operation S130, which is performed in response to determining the read error S120; fig. 12, 13, 16);
determining a first voltage offset (an offset voltage level may be selected from offset table S1330; fig. 16, detailed offset table β; fig. 14B, para 0129) corresponding to the first use state (S1330 corresponding to the first degradation state; fig. 16) according to a preset mapping relationship (fig. 15); and
obtaining at least one first read voltage (S134; fig. 13) used for performing a read operation on the memory device (S135; fig. 13) in the first use state according to a preset reference read voltage (i.e. default read voltage) and the first voltage offset (para 0119),
wherein the preset mapping relationship includes corresponding relationships (para 0130) between different use states (different degradation states, i.e. the first degradation state having the degradation parameter value in RANGE 1, a different degradation state having another degradation parameter value in RANGE 2; fig. 15) of the memory device and respective voltage offsets (RANGE 1 in relation to offset β1, RANGE 2 in relation to offset β2; fig. 15), and the first voltage offset (i.e. the offset voltage level) comprises a first offset value (any offset value among values corresponding to R1-RN with respect to read voltages RP1-RP7; fig. 14B) relative to the preset reference read voltage (i.e. default read voltage), wherein each of the different use states (i.e. each degradation state) is based on a respective set of state parameters (degradation parameter(s), i.e. for accessing the memory in program, erase, read operations; para 0147) associated with one or more operations of the memory device (para 0046), and wherein the state parameters of the memory device comprise at least one of an erase count, a program count (P/E count; para 0142), a read count, a read temperature, a program temperature, or a program to read time interval of the memory device (i.e. “degradation parameter may include at least one selected from the group consisting of the number of error bits in data read based on an optimal read voltage set, temperature of a non-volatile memory, and a read count of the non-volatile memory” para 0145).
Regarding claim 12, Ahn discloses the memory controller, wherein the preset mapping relationship is stored in the memory device (para 0142), wherein the operations further comprise: sending a first read command (CMD; fig. 1) to the memory device (200); receiving the preset mapping relationship (fig. 15) fed back (i.e. loaded to memory controller 110; para 0142) by the memory device in response to the first read command (para 00048-0050, 0064) and buffering (i.e. caching) the preset mapping relationship to the at least one memory (para 0041).
Regarding claim 19, Ahn discloses a memory system, comprising:
one or more memory devices (120; fig. 1, further detailed 200; fig. 2); and
a memory controller (110; fig. 1) coupled with the one or more memory devices (200) and configured to control the one or more memory devices, wherein the memory controller is configured to:
determine (fig. 16) that a memory device (200; fig. 1) is in a first use state (a first degradation state, having “a degradation parameter value [i.e. use state] corresponding to a selected memory block may be identified in operation S1300” para 0147) in response to determining (S120; fig. 12) that a read error is occurred (a read error occurred in a first read operation; para 0118) in the memory device (the memory device is determined to be in the first degradation state (YES S1310) as part of a second read operation S130, which is performed in response to determining the read error S120; fig. 12, 13, 16);
determine a first voltage offset (an offset voltage level may be selected from offset table S1330; fig. 16, detailed offset table β; fig. 14B, para 0129) corresponding to the first use state (S1330 corresponding to the first degradation state; fig. 16) according to a preset mapping relationship (fig. 15); and
obtain at least one first read voltage (S134; fig. 13) for performing a read operation on the memory device (S135; fig. 13) in the first use state according to a preset reference read voltage (i.e. default read voltage) and the first voltage offset (para 0119),
wherein the preset mapping relationship includes corresponding relationships (para 0130) between different use states (different degradation states, i.e. the first degradation state having the degradation parameter value in RANGE 1, a different degradation state having another degradation parameter value in RANGE 2; fig. 15) of the memory device and respective voltage offsets (RANGE 1 in relation to offset β1, RANGE 2 in relation to offset β2; fig. 15), and the first voltage offset (i.e. the offset voltage level) comprises a first offset value (any offset value among values corresponding to R1-RN with respect to read voltages RP1-RP7; fig. 14B) relative to the preset reference read voltage (i.e. default read voltage), wherein each of the different use states (i.e. each degradation state) is based on a respective set of state parameters (degradation parameter(s), i.e. for accessing the memory in program, erase, read operations; para 0147) associated with one or more operations of the memory device (para 0046), and wherein the state parameters of the memory device comprise at least one of an erase count, a program count (P/E count; para 0142), a read count, a read temperature, a program temperature, or a program to read time interval of the memory device (i.e. “degradation parameter may include at least one selected from the group consisting of the number of error bits in data read based on an optimal read voltage set, temperature of a non-volatile memory, and a read count of the non-volatile memory” para 0145).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US 2024/0069790 “Ahn”) in view of Kiyooka et al. (US 2023/0096401 “Kiyooka”).
Regarding claim 2, Ahn discloses an operation method, wherein the first voltage offset comprises one or more first voltage offset values, and the at least one first read voltage comprises one or more first read voltages (fig. 14B, 15).
Ahn does not expressly disclose and wherein the operation method further comprises: selecting at least one of the one or more first read voltages as a soft read reference voltage of soft decoding; for each soft read reference voltage, obtaining a corresponding set of soft read voltages including the soft read reference voltage according to the soft read reference voltage and a preset offset rule; and performing the soft decoding on the memory device according to at least one set of soft read voltages.
Kiyooka discloses selecting at least one of the one or more first read voltages (i.e. of a read voltage set; para 0042) as a soft read reference voltage of soft decoding (para 0042); for each soft read reference voltage (hard read voltage Rn functions as a reference voltage for soft read(s); fig. 6), obtaining a corresponding set of soft read voltages (R(n)r1, R(n)r2, R(n)r3 and R(n)r4; fig. 6) including the soft read reference voltage according to the soft read reference voltage and a preset offset rule (i.e. offset that is shifted by r1, r2, r3 and r4; fig. 6); and performing the soft decoding on the memory device according to at least one set of soft read voltages (fig. 8, 9).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Ahn is modifiable as taught by Kiyooka for the purpose of facilitating data accessing schemes by increasing overall success of decoding, which is common and well known in the art to improve error correction schemes (para 0056, 0107 of Kiyooka).
Regarding claim 13, Ahn discloses the memory controller, wherein the first voltage offset comprises one or more first voltage offset values, and the at least one first read voltage comprises one or more first read voltages (fig. 14B, 15).
Ahn does not expressly disclose and wherein the operation method further comprises: selecting at least one of the one or more first read voltages as a soft read reference voltage of soft decoding; for each soft read reference voltage, obtaining a corresponding set of soft read voltages including the soft read reference voltage according to the soft read reference voltage and a preset offset rule; and performing the soft decoding on the memory device according to at least one set of soft read voltages.
Kiyooka discloses selecting at least one of the one or more first read voltages (i.e. of a read voltage set; para 0042) as a soft read reference voltage of soft decoding (para 0042); for each soft read reference voltage (hard read voltage Rn functions as a reference voltage for soft read(s); fig. 6), obtaining a corresponding set of soft read voltages (R(n)r1, R(n)r2, R(n)r3 and R(n)r4; fig. 6) including the soft read reference voltage according to the soft read reference voltage and a preset offset rule (i.e. offset that is shifted by r1, r2, r3 and r4; fig. 6); and performing the soft decoding on the memory device according to at least one set of soft read voltages (fig. 8, 9).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Ahn is modifiable as taught by Kiyooka for the purpose of facilitating data accessing schemes by increasing overall success of decoding, which is common and well known in the art to improve error correction schemes (para 0056, 0107 of Kiyooka).
Allowable Subject Matter
Claim(s) 3-10, 14-18, 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 3 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely putting the memory device in different use states; obtaining a Read Retry Table (RRT) from the memory device in each use state; traversing the RRT, performing a read operation on the memory device one by one, and obtaining at least one voltage offset in the corresponding RRT when a read error meets a preset condition; and establishing a corresponding relationship between each of the use states and the corresponding at least one voltage offset; and generating the mapping table according to each corresponding relationship.
With respect to dependent claim 8, the prior art fails to teach or suggest the claimed limitations, namely determining a set of hard read voltages according to the preset reference read voltage and a Read Retry Table (RRT) before determining that the memory device is currently in the first use state, wherein the set of hard read voltages comprises a default read voltage and a plurality of re-read voltages, and the plurality of re-read voltages have a predetermined offset from the preset reference read voltage; and performing hard decoding on the memory device according to the set of hard read voltages.
With respect to dependent claim 9 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely performing the soft decoding on the memory device gradually according to one set of soft read voltages of a plurality of sets of soft read voltages; and finishing the soft decoding on the memory device until at least one of the soft decoding passes or the number of times of performing the soft decoding reaches a preset threshold value.
With respect to dependent claim 14 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely putting the memory device in different use states; in each use state, traversing the RRT in the memory, performing a read operation on the memory device one by one, and obtaining at least one voltage offset in the corresponding RRT when a read error meets a preset condition; establishing a corresponding relationship between each of the use states and the corresponding at least one voltage offset; and generating the mapping table according to each corresponding relationship.
With respect to dependent claim 20, the prior art fails to teach or suggest the claimed limitations, namely access the register to obtain the set of voltage offsets, obtain the set of soft read voltages according to a preset reference read voltage and the set of voltage offsets, and gradually provide each soft read voltage of the set of soft read voltages to selected word lines corresponding to selected memory cells included in the memory array to obtain a corresponding set of soft read data, and wherein the memory device is further configured to: perform soft decoding on the set of soft read data.
The allowable claims are supported in at least fig. 7-8 of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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