DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim.
Applicant’s election of claims 1-10 in the reply filed on 07/06/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 10 is/are objected to because of the following informalities:
Claim 10 recites “EG wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region” in Lines L5-6 but should read –EG wherein MP refers to a density of bump pads that are disposed on the center region and EG refers to a density of bump pads that are disposed on the edge region --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the limitation "the planar area of the bump structure" in Line L2, renders the claim indefinite because the antecedent basis is unclear as to whether “the planar area of the bump structure” (Line L2) refers to a new planar area of the bump structure or one of the “planar areas” previously cited in Line L6 of Claim 1. In the purpose of compact prosecution, “the planar area of the bump structure” has been interpretated as a planar area of the bump structure.
Regarding claim 7, the limitation "the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip" in Lines L2-3, renders the claim indefinite because the antecedent basis is unclear as to whether “the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip” (Lines L2-3) refers to new surface areas of the bump pads and new surface area of either the first or second semiconductor chip or the “planar areas” previously cited in Line L6 of Claim 1. In the purpose of compact prosecution, “the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip” has been interpretated as a surface area of the bump pads, including the extension portions, to a surface area of either the first or second semiconductor chip.
Regarding claim 9, the limitation "densities on the center regions” (Lines L2-3) renders the claim indefinite because the antecedent basis is unclear as to whether "densities on the center regions” (Lines L2-3) refers to densities of the bump pads on the center regions or densities of the bump structures on the center regions similar to “densities of the bump structures on the edge regions” previously cited in Line L2. In the purpose of compact prosecution, “densities on the center regions” has been interpretated as densities of the bump structures on the center regions.
Regarding claim 10, the limitation "wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region” (Lines L6-7) renders the claim indefinite because the antecedent basis is unclear as to whether wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region” (Lines L6-7) refers to new density of bump pads that are disposed on the center region and new density of bump pads that are disposed on the edge region or the “densities” previously cited in Line L2 of Claim 9. In the purpose of compact prosecution, “wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region” has been interpretated as wherein MP refers to a density of bump pads that are disposed on the center region and EG refers to a density of bump pads that are disposed on the edge region.
The balance of claims is rejected for being dependent upon an already rejected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (US20230029151A1-Noh51).
Regarding claim 1, Noh51 discloses a semiconductor package (Title), comprising:
a first semiconductor chip (first semiconductor chip 10-Fig 1).
a second semiconductor chip disposed on the first semiconductor chip (Second semiconductor chip 20 disposed on the first semiconductor chip 10-Fig 1); and
at least one bump structure disposed between the first semiconductor chip and the second semiconductor chip (bump structure 23/35/13 disposed between the first semiconductor chip 10 and the second semiconductor chip 20-Fig 1),
wherein the bump structure includes a first bump pad and a second bump pad with different planar areas (Bump structure 23/35/13 including a first bump pad 23 and a second bump pad 23 with planar/horizontal area of first bump pad 13 being larger than planar/horizontal area of second bump pad 23, so with different planar areas-Fig 1).
Regarding claim 2, Noh51 discloses all the elements of claim 1, as noted above.
Noh51 further discloses a semiconductor package
wherein the planar area of the bump structure is in contact with either the first semiconductor chip or the second semiconductor chip (planar/horizontal area of first bump pad 13 being in contact with first semiconductor chip 10 and planar/horizontal area of second bump pad 23 being in contact with second semiconductor chip 20-Fig 1).
Regarding claim 3, Noh51 discloses all the elements of claim 1, as noted above.
Noh51 further discloses a semiconductor package
wherein either the first bump pad or the second bump pad includes an extension portion that extends horizontally in at least one direction (First bump pad 13 with Horizontal Right extension 13E2 and Vertical Left extension 13E1-Examiner's annotated Fig 1),
wherein the direction includes a first direction (Horizontal extending in the Right direction-Fig 1),
a direction opposite to the first direction (Horizontal extending in the Left direction so opposite to the first direction-Fig 1),
a second direction intersecting the first direction in a horizontal direction (z-direction going up-Fig 1); and
a direction opposite to the second direction (z-direction going down-Fig 1);
wherein the extension portion extends from the first bump pad or the second bump pad (First bump pad 13 with Horizontal extending in the Right direction extension 13E2 and Vertical extending in the Left direction extension 13E1-Examiner's annotated Fig 1).
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Regarding claim 4, Noh51 discloses all the elements of claim 2, as noted above.
Noh51 further discloses a semiconductor package
wherein the first bump pad or the second bump pad including an extension portion has a larger planar area (First bump pad 13 with a larger horizontal planar area as indicated by arrow with extension 13E1 and 13E2-Examiner's annotated Fig 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US20230029151A1-Noh51) in view of Chen et al. (US20190123006A1-Chen06).
Regarding claim 5, Noh51 discloses all the elements of claim 2, as noted above.
Noh51 does not disclose a semiconductor package
wherein a width-to-height ratio of either the first bump pad or the second bump pad including the extension portion is equal to or greater than 7.5.
However, Noh51 teaches that increasing the width of the extension 13E so increasing the width-to-height ratio, reduces the thermal stress on the system (Noh51: [0044]- [0048], Fig 2).
Chen06 recognizes that there is a need for improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size (Chen06: [0002]).
The width-to-height ratio of either the first bump pad or the second bump pad is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the width-to-height ratio of either the first bump pad or the second bump pad as it has been identified as a result effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the width-to-height ratio of either the first bump pad or the second bump pad being equal to or greater than 7.5, in order to achieve the desired balance in pad width between reducing the thermal stress on the system as taught by Noh51 and improving the integration density as taught by Chen06. (see MPEP 2144.05.II). Furthermore, the applicant has not presented persuasive evidence that the claimed relative width-to-height ratio of either the first bump pad or the second bump pad is for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative width-to-height ratio of either the first bump pad or the second bump pad).
Regarding claim 6, Noh51 discloses all the elements of claim 2, as noted above.
Noh51 does not disclose a semiconductor package
wherein a length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip is within a range greater than 0 and less than or equal to 0.8 μm.
However, Noh51 teaches that increasing the width of the extension 13E reduces the thermal stress on the system (Noh51: [0044]- [0048], Fig 2).
Chen06 recognizes that there is a need for improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size (Chen06: [0002]).
The length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip as it has been identified as a result effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip being within a range greater than 0 and less than or equal to 0.8 μm, in order to achieve the desired balance in pad width between reducing the thermal stress on the system as taught by Noh51 and improving the integration density as taught by Chen06. (see MPEP 2144.05.II). Furthermore, the applicant has not presented persuasive evidence that the claimed relative length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip is for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative length of the extension portion disposed parallel to the front surface of either the first semiconductor chip or the second semiconductor chip).
Regarding claim 7, Noh51 discloses all the elements of claim 2, as noted above.
Noh51 does not disclose a semiconductor package
wherein a ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip is within a range of 2.05% to 3.50%.
However, Noh51 teaches that increasing the width of the extension 13E reduces the thermal stress on the system (Noh51: [0044]- [0048], Fig 2).
Chen06 recognizes that there is a need for improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size (Chen06: [0002]).
The ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to vary, through routine optimization, the ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip as it has been identified as a result effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip being within a range of 2.05% to 3.50%, in order to achieve the desired balance in pad width between reducing the thermal stress on the system as taught by Noh51 and improving the integration density as taught by Chen06. (see MPEP 2144.05.II). Furthermore, the applicant has not presented persuasive evidence that the claimed relative ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip is for a purpose that is critical to the overall claimed invention (i.e. that the invention would be inoperable without the specified claimed relative ratio of the surface area of the bump pads, including the extension portions, to the surface area of either the first or second semiconductor chip).
Regarding claim 8, Noh51 discloses all the elements of claim 2, as noted above.
Noh51 does not disclose a semiconductor package
wherein rear surfaces of the first semiconductor chip and the second semiconductor chip include
center regions and
edge regions,
wherein the edge regions surround the center regions and
occupy a length ratio of 15% to 25% from side surfaces of the first semiconductor chip and the second semiconductor chip.
Chen06 teaches a semiconductor package
wherein rear surfaces of the first semiconductor chip and the second semiconductor chip include
center regions (center regions 150-Fig 1A) and
edge regions (edge regions 152-Fig 1A),
wherein the edge regions surround the center regions (edge regions 152 surrounding the center regions 150-Fig 1A) and
occupy a length ratio of 15% to 25% from side surfaces of the first semiconductor chip and the second semiconductor chip ( length ration between pad width 144 and the chip length 140 or chip width 142 is equal to or less than 10%, so the Edge regions length ratio is twice this ratio or equal to or less than 20%-[0046] L19-21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of Noh51 as taught by Chen06 for the purpose of improving the integration density (Chen06: [0002]).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US20230029151A1-Noh51) in view of Jeng et al. (US20210242122A1-Jeng22).
Regarding claim 9, Noh51 discloses all the elements of claim 1, as noted above.
Noh51 does not disclose a semiconductor package
wherein densities of the bump structures on the edge regions are higher than densities on the center regions.
Jeng22 teaches a semiconductor package
wherein densities of the bump structures on the edge regions are higher than densities on the center regions (center region density is 0 so lower than the density on the edge region with the bumps 173b-Fig 8B).
It would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of Noh51 as taught by Jeng22 for the purpose of preventing stress caused by thermal expansion mismatch so decreasing chip warpage (Jeng22: [0074] [0122]).
Regarding claim 10, Noh51 discloses all the elements of claim 10, as noted above.
Noh51 does not disclose a semiconductor package
wherein densities of the bump pads including the extension portions satisfies the following Expression 1: <Expression 1 > MP × 1.5 < EG
wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region.
Jeng22 teaches a semiconductor package
wherein densities of the bump pads including the extension portions satisfies the following Expression 1: <Expression 1 > MP × 1.5 < EG ( the density of bump pads that are disposed on the edge region EG is not zero, while the density of bump pads MP that are disposed on the center region is zero, so MP × 1.5 < EG -Fig 8B).
wherein MP refers to the density of bump pads that are disposed on the center region and EG refers to the density of bump pads that are disposed on the edge region (the density of bump pads that are disposed on the edge region EG is not zero, while the density of bump pads MP that are disposed on the center region is zero, so MP × 1.5 < EG -Fig 8B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of Noh51 as taught by Jeng22 for the purpose of preventing stress caused by thermal expansion mismatch so decreasing chip warpage (Jeng22: [0074] [0122]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 08/18/2026/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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