Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-8, 10, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20130069239 to Kim et al. (Kim), or alternatively Kim in view of U.S. Pat. No. 9461018. to Tsai et al. (Tsai).
Regarding Claim 1, Kim teaches in Fig. 18 at least, apparatus, comprising:
a structure wafer 650;
a first die 188 bonded to the structure wafer by a bonding layer 622;
a first metallization structure 184 disposed below and electrically coupled to the first die opposite the structure wafer;
fill material 640 disposed between the structure wafer and the first metallization structure, wherein the fill material embeds the first die;
a second metallization structure 656 disposed on top of the structure wafer, wherein the second metallization structure comprises a second inorganic dielectric layer 654
a second die 680 disposed on top of the second metallization structure and electrically coupled to the second metallization structure by a plurality of die connectors 688; and
a plurality of through-substrate vias 648/722 configured to electrically couple the first metallization structure to the second metallization structure.
Kim shows a single rather than a plurality of second dielectric layers. However, such lamination layers of an RDL can easily be duplicated by the person of ordinary skill to increase wiring density (MPEP 2144.04(VI)(B)). Alternatively, Tsai teaches that an RDL may have multiple layers of dielectric 56 and metal and vias therebetween. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Tsai to increase wiring density.
Regarding Claim 2, Kim or Kim and Tsai teach the apparatus of claim 1, wherein the plurality of die connectors comprises solder balls 688.
Regarding Claim 4, Kim or Kim and Tsai teach the apparatus of claim 1, wherein the plurality of through-substrate vias is disposed outside the first die and traverses the fill material and the structure wafer (See Fig. 18).
Regarding Claim 5, Kim or Kim and Tsai teach the apparatus of claim 1, wherein the first metallization structure further comprises:
a first plurality of dielectric layers 174;
a first plurality of metal layers 176 disposed in the first plurality of dielectric layers; and
a first plurality of vias 172 configured to couple adjacent metal layers of the first plurality of metal layers through the first plurality of dielectric layers.
Regarding Claim 6, Kim or Kim and Tsai teach the apparatus of claim 5, wherein the first plurality of dielectric layers comprises:
inorganic dielectric layers (described as an insulator, and insulator is defined as inorganic in [0057]).
Regarding Claim 7, or Kim and Tsai teach the apparatus of claim 6, wherein the first plurality of dielectric layers comprises:
silicon (Si), gallium arsenide (GaAs), or silicon germanium (SiGe) [0057].
Regarding Claim 8, Kim or Kim and Tsai teach the apparatus of claim 5, wherein the first plurality of dielectric layers comprises:
organic dielectric layers (Tsai teaches RDL insulators may be organic or inorganic 5:8-16).
Regarding Claim 10, or Kim and Tsai teach the apparatus of claim 1, wherein the second metallization structure further comprises:
a second plurality of metal layers disposed in the second plurality of inorganic dielectric layers; and
a second plurality of vias configured to couple adjacent metal layers of the second plurality of metal layers through the second plurality of inorganic dielectric layers (although one layer each of insulator 654 and metal 656 are shown, they may easily be duplicated to increase wiring density, necessitating through vias, forming a well-known RDL, see also teaching of Tsai).
Regarding Claim 11, Kim or Kim and Tsai teach the apparatus of claim 10, wherein the second plurality of inorganic dielectric layers comprise silicon (Si) [0057], gallium arsenide (GaAs), or silicon germanium (SiGe).
Regarding Claim 15, Kim or Kim and Tsai teach the apparatus of claim 1, wherein the apparatus comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle [0042].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim and Tsai as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20230207437 to Haba.
Regarding Claim 3, Kim or Kim and Tsai teach the apparatus of claim 1, but do not explicitly teach that the plurality of die connectors comprises hybrid bonded contacts.
However, in analogous art, Haba teaches that hybrid bonding over solder ball bonding [0026]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Haba for a thinner form factor as taught by Haba in the quoted section.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim and Tsai as applied to claim 8 above, and further in view of U.S. Pat. Pub. No. 20160181361 to Shea.
Regarding Claim 9, Kim or Kim and Tsai teach the apparatus of claim 8, but do not explicitly teach that the first plurality of dielectric layers comprises:
fiberglass impregnated with resin (prepreg) (Tsai teaches PBO, 5:12, Shea teaches that PBO and prepreg are interchangeable in an RDL, see MPEP 2144.06-07), Ajinomoto build-up film (ABF), or a resin coated copper (RCC) build-up film.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim or Kim and Tsai as applied to claim 8 above, and further in view of U.S. Pat. Pub. No. 20100058580 to Yazdani.
Regarding Claims 12 and 13, Kimor Kim and Tsai teach the apparatus of claim 8, but do not explicitly teach that at least one of the first metallization structure or the second metallization structure further comprises:
one or more integrated passive devices such as one or more capacitors; one or more inductors; or combinations thereof.
However, in analogous art, Yazdani teaches that an RDL may include passives such as capacitors. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Yazdani to increase integration, a constant driving force in semiconductor manufacturing.
Claims 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 11417629 to Chen et al. (Chen) or alternatively Chen in view of Kim.
Regarding Claim 1, Chen teaches in Fig. 5 at least, apparatus, comprising:
a structure wafer (unlabeled element directly above over mold 52);
a first die 300 bonded to the structure wafer by a bonding layer (unlabeled bonding layer directly over 300/400);
a first metallization structure 53 disposed below and electrically coupled to the first die opposite the structure wafer;
fill material 52 disposed between the structure wafer and the first metallization structure, wherein the fill material embeds the first die;
a second die 57 disposed on top of the second metallization structure and electrically coupled to the second metallization structure by a plurality of die connectors 58; and
a plurality of through-substrate vias 51 configured to electrically couple the first metallization structure to the second metallization structure.
Chen does not explicitly teach a second metallization structure disposed on top of the structure wafer, wherein the second metallization structure comprises a second inorganic dielectric layer. However, it would have been obvious to the person of ordinary skill in the art before the time of filing to duplicate the RDL 53 on a top surface of the wafer structure to increase wiring density and enable greater flexibility of IC footprint/ layout.
Alternatively, Kim teaches a second metallization structure as described above. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Kim for the same reason.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen or Chen and Kim as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. 20160071818 to Wang et al. (Wang).
Regarding Claim 14, Chen or Chen and Kim teach the apparatus of claim 1, further comprising:
a die underfill (unlabeled underfill surrounding solder balls 58) disposed between the second die and the second metallization structure, but do not explicitly teach that the die underfill and the fill material each comprise an organic material.
Chen is silent regarding the materials. However, in analogous art, Wang teaches that underfill and mold may be organic [0083,0120]. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Wang to complete and fully practice the invention of Chen.
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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