CTNF 18/438,450 CTNF 90717 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch(USPGPUB DOCUMENT: 2008/0150125, hereinafter Braunisch) in view of Panella (USPGPUB DOCUMENT: 2003/0193791, hereinafter Panella) . Re claim 1 Braunisch discloses a computing system comprising: a board assembly including a die(108/126) and a circuit board(104) electrically coupled to a first side(top/bottom) of the die(108/126); and a thermal dissipation assembly(118/202/116) thermally and electrically coupled to a second side(top/bottom) of the die(108/126), wherein the thermal dissipation assembly(118/202/116) is further electrically coupled to the voltage regulator. Braunisch does not disclose a voltage regulator; wherein the thermal dissipation assembly(118/202/116) is further electrically coupled to the voltage regulator. Panella disclose a voltage regulator(38 of Panella)[0257]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Panella to the teachings of Braunisch in order to increases in the functionality and performance of integrated circuit (IC) devices while minimizing the size, weight, defects and cost of the IC devices[0004, Panella]. In doing so, wherein the thermal dissipation assembly(118/202/116) is further electrically coupled to the voltage regulator(38 of Panella). Re claim 2 Braunisch and Panella disclose the computing system of claim 1, wherein the thermal dissipation assembly(118/202/116) provides a power delivery path from the voltage regulator(38 of Panella) to the second side(top/bottom) of the die(108/126). Re claim 3 Braunisch and Panella disclose the computing system of claim 2, wherein the thermal dissipation assembly(118/202/116) further provides a ground connection from the second side(top/bottom) of the die(108/126) to the voltage regulator(38 of Panella). Re claim 4 Braunisch and Panella disclose the computing system of claim 1, wherein the circuit board(104) provides a ground connection from the first side(top/bottom) of the die(108/126) to the voltage regulator(38 of Panella). Re claim 5 Braunisch and Panella disclose the computing system of claim 1, wherein the voltage regulator(38 of Panella) is mounted to the thermal dissipation assembly(118/202/116) or the circuit board(104). Re claim 6 Braunisch and Panella disclose the computing system of claim 1, further comprising a regulator board electrically coupled to the thermal dissipation assembly(118/202/116), wherein the voltage regulator(38 of Panella) is mounted to the regulator board. Re claim 7 Braunisch and Panella disclose the computing system of claim 1, further comprising: a plurality of signal contacts electrically coupled to the circuit board(104); and a package substrate(106/102) electrically coupled to the plurality of signal contacts and the first side(top/bottom) of the die(108/126); wherein the voltage regulator(38 of Panella) is mounted to the package substrate(106/102). Re claim 8 Braunisch and Panella disclose the computing system of claim 1, wherein the second side(top/bottom) of the die(108/126) includes a plurality of power contacts. Re claim 9 Braunisch and Panella disclose the computing system of claim 1, wherein the thermal dissipation assembly(118/202/116) includes a heat sink, a heat spreader, or a vapor chamber. Re claim 10 Braunisch and Panella disclose the computing system of claim 9, wherein the thermal dissipation assembly(118/202/116) includes the vapor chamber, and wherein the computer system further comprises a plurality of copper plates(plated copper)[0017] electrically coupled to the voltage regulator(38 of Panella) and a package substrate(106/102) containing the die(108/126), wherein the plurality of copper plates(plated copper)[0017] are further thermally coupled to the vapor chamber. Re claim 11 Braunisch and Panella disclose the computing system of claim 10, wherein individual copper plates(plated copper)[0017] of the plurality of copper plates(plated copper)[0017] provide a dedicated power delivery rail from the voltage regulator(38 of Panella) to the package substrate(106/102). Re claim 12 Braunisch and Panella disclose the computing system of claim 10, wherein a first end of the respective copper plates(plated copper)[0017] includes a pogo pin electrically coupled to the package substrate(106/102), and wherein a second end of the respective copper plates(plated copper)[0017] includes a spring clip that mates with a terminal of a charge storage device associated with the voltage regulator(38 of Panella). Re claim 13 Braunisch and Panella disclose the computing system of claim 10, further comprising: a thermally conductive adhesive positioned between the thermal dissipation assembly(118/202/116) and the plurality of copper plates(plated copper)[0017]; or a copper pedestal positioned between the vapor chamber and the second side(top/bottom) of the die(108/126). Re claim 14 Braunisch discloses in Fig 1, rotated 180 degrees, an apparatus comprising: a board assembly including a die(108/126) and a circuit board(104) electrically coupled to a first side(top/bottom) of the die(108/126); a thermal dissipation assembly(118/202/116); and a plurality of copper plates(plated copper)[0017] and a package substrate(106/102) containing the die(108/126), wherein the plurality of copper plates(plated copper)[0017] are further thermally coupled to the thermal dissipation assembly(118/202/116). Braunisch does not disclose wherein the circuit board(104) includes a voltage regulator; a thermal dissipation assembly(118/202/116); and a plurality of copper plates(plated copper)[0017] electrically coupled to the voltage regulator and a package substrate(106/102) containing the die(108/126), Panella disclose wherein the circuit board(114)[0257] includes a voltage regulator(38 of Panella); It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Panella to the teachings of Braunisch in order to increases in the functionality and performance of integrated circuit (IC) devices while minimizing the size, weight, defects and cost of the IC devices[0004, Panella]. In doing so, a thermal dissipation assembly(118/202/116); and a plurality of copper plates(plated copper)[0017] electrically coupled to the voltage regulator(38 of Panella) and a package substrate(106/102) containing the die(108/126), Re claim 15 Braunisch and Panella disclose the apparatus of claim 14, wherein individual copper plates(plated copper)[0017] of the plurality of copper plates(plated copper)[0017] provide a dedicated power delivery rail from the voltage regulator(38 of Panella) to the package substrate(106/102). Re claim 16 Braunisch and Panella disclose the apparatus of claim 14, wherein the respective copper plates(plated copper)[0017] include a pogo pin electrically coupled to the package substrate(106/102). Re claim 17 Braunisch and Panella disclose the apparatus of claim 14, wherein the respective copper plates(plated copper)[0017] include a spring clip that mates with a terminal of a charge storage device associated with the voltage regulator(38 of Panella). Re claim 18 Braunisch and Panella disclose the apparatus of claim 14, further comprising a thermally conductive adhesive positioned between the thermal dissipation assembly(118/202/116) and the plurality of copper plates(plated copper)[0017]. Re claim 19 Braunisch and Panella disclose the apparatus of claim 14, further comprising a copper pedestal positioned between the thermal dissipation assembly(118/202/116) and a second side(top/bottom) of the die(108/126). Re claim 20 Braunisch and Panella disclose the apparatus of claim 14, wherein the thermal dissipation assembly(118/202/116) includes a vapor chamber. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812 Application/Control Number: 18/438,450 Page 2 Art Unit: 2812 Application/Control Number: 18/438,450 Page 3 Art Unit: 2812 Application/Control Number: 18/438,450 Page 4 Art Unit: 2812 Application/Control Number: 18/438,450 Page 5 Art Unit: 2812 Application/Control Number: 18/438,450 Page 6 Art Unit: 2812 Application/Control Number: 18/438,450 Page 7 Art Unit: 2812 Application/Control Number: 18/438,450 Page 8 Art Unit: 2812
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