DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 8, 2026 have been fully considered but they are not persuasive.
The Applicant asserts that the combination of Wutte and Liu fail to disclose the limitations of claim 1 as applied in the previous Office Action. Specifically, that Liu fails to disclose the vertical transistor device and the MGD arranged consecutively in the first lateral direction because “all lateral extensions of Liu's gate trench structures 104 are the same. Therefore, none of the lateral extensions of Liu's gate trench structures 104 can be considered elongated relative to the other lateral extensions.”
The Examiner respectfully disagrees that the combination of Wutte and Liu fails to disclose the limitations of claim 1. While Liu does not disclose a lateral extension, Figs. 1-2 of Liu show that the vertical transistors and the MGD are arranged consecutively in two perpendicular directions. The first direction is along the A-A’ line of Fig. 1, which is further shown in Fig. 2. The second is the direction perpendicular to the A-A’ line. Fig. 10A of Wutte shows that the vertical transistor and the MGD are arranged consecutively in a second lateral direction that is perpendicular to the first lateral direction. Incorporating the teachings of Liu such that they alternate in two directions perpendicular to each other would necessarily result in a structure where the vertical transistors and the MGD are arranged consecutively in the first lateral direction.
Therefore, the Examiner asserts that the combination of Wutte and Liu disclose the limitations of claim 1 as applied in the previous Office Action. The rejection is maintained as appropriate and presented in full herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wutte et al. (US 20180226481 A1) herein after “Wutte” in view of Liu et al. (US 20200168719 A1) herein after “Liu”.
Regarding claim 1, Figs. 3 and 4A of Wutte disclose a semiconductor die (Fig. 3, semiconductor device, ¶ [0058]), comprising:
a vertical transistor device (Fig. 4A, transistor cells 380, ¶ [0052]) having a gate electrode (Fig. 4A, gate electrode 360, ¶ [0052]) in a gate trench (Fig. 4A, first sections 110 of the first gate trenches 100, ¶ [0054]); and
a MOS gated diode (MGD) (“the gate electrode 360 in the first trench 100… is interrupted and electrically connected to the source metal layer 530 to form a MOS gated-diode”, ¶ [0080]) having an MGD gate electrode (360) in an MGD trench (110),
wherein the gate trench (110) has an elongated extension in a first lateral direction (horizontal direction in Fig. 3).
Wutte fails to explicitly disclose wherein the vertical transistor device and the MGD are arranged consecutively in the first lateral direction.
In the similar field of endeavor of semiconductor devices, Figs. 1-2 of Liu disclose wherein the vertical transistor device (Fig. 2, transistor cells 102, ¶ [0025]) and the MGD (Fig. 2, MGD 126, ¶ [0029]) are arranged consecutively in the first lateral direction (A-A’ direction in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wutte with the transistor and MGD arrangement as disclosed by Liu, to reduce parasitic inductance and increase switching frequency (see Liu, ¶ [0022-0023]).
Regarding claim 2, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Fig. 3 of Wutte further discloses wherein the gate electrode (360) and the MGD gate electrode (360) are arranged on a common straight line which lies parallel to the first lateral direction (horizontal direction in Fig. 3).
Regarding claim 3, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Wutte further discloses wherein the gate electrode (360) and the MGD gate electrode (360) are arranged in different portions of a continuous trench (“A gate electrode 360 may be disposed in the first… gate trench 100”, ¶ [0052]).
Regarding claim 4, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Figs. 4A-4B of Wutte further disclose wherein the vertical transistor device (380) also has an elongated field electrode (Fig. 4A, field plate 370, ¶ [0052]) in the gate trench (110) below the gate electrode (360), and wherein the field electrode (370) is connected laterally between the vertical transistor device (380) and the MGD to a frontside contact (Fig. 4B, conductive layer 530, ¶ [0051]).
Regarding claim 5, Wutte and Liu together disclose the semiconductor die of claim 4 as applied above, and Figs. 4A-4B of Wutte further disclose wherein the gate electrode (360) and the MGD gate electrode (360) are arranged in different portions of a continuous trench (100), and wherein the field electrode (370) is made of a field electrode material, and wherein the field electrode material extends continuously in the continuous trench (“A field plate 370 may be disposed in a lower portion of the first gate trench 100”, ¶ [0052]).
Regarding claim 6, Wutte and Liu together disclose the semiconductor die of claim 4 as applied above, and Wutte further discloses wherein the MGD gate electrode (360) is connected to the frontside contact (“the gate electrode 360 in the first trench 100… is interrupted and electrically connected to the source metal layer 530 to form a MOS gated-diode”, ¶ [0080]).
Regarding claim 7, Wutte and Liu together disclose the semiconductor die of claim 4 as applied above, and Wutte further discloses wherein the gate electrode (360) and the MGD gate electrode (360) are arranged in different portions of a continuous trench (“A gate electrode 360 may be disposed in the first and the second gate trench 100”, ¶ [0052]), wherein the gate electrode (360) and the MGD gate electrode (360) are made of the same gate electrode material, and wherein the gate electrode material is arranged in the continuous trench (100) and interrupted between the different portions of the continuous trench (“the gate electrode 360 in the first trench 100… is interrupted and electrically connected to the source metal layer 530 to form a MOS gated-diode”, ¶ [0080]).
Regarding claim 8, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Fig. 4A of Wutte further discloses wherein a body region (Fig. 4A, body region 353, ¶ [0052]) of the vertical transistor device (380) and an MGD body region (353) of the MGD are different portions of a continuous implant region (“The doped portion 307 of the second conductivity type forms the body region 353”, ¶ [0052]).
Regarding claim 9, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Fig. 4A of Wutte further discloses wherein a body region (353) of the vertical transistor device (380) is connected to a frontside contact (530) by a vertical interconnect (Fig. 4A, contacts 376, ¶ [0060]), and wherein an MGD body region (353) of the MGD is connected to the frontside contact (530) by an MGD vertical interconnect (376) of a same type as the vertical interconnect (376) of the vertical transistor device (380).
Regarding claim 10, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, but Wutte fails to explicitly disclose wherein a respective vertical transistor device is arranged on both sides of the MGD in the first lateral direction.
In the similar field of endeavor of semiconductor devices, Figs. 1-2 of Liu disclose wherein a respective vertical transistor device (102) is arranged on both sides of the MGD (126) in the first lateral direction (A-A’ direction in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wutte with the transistor and MGD arrangement as disclosed by Liu, to reduce parasitic inductance and increase switching frequency (see Liu, ¶ [0022-0023]).
Regarding claim 11, Wutte and Liu together disclose the semiconductor die of claim 1 as applied above, and Fig. 4A of Wutte further discloses wherein in a vertical cross-section perpendicular to the first lateral direction (horizontal direction in Fig. 3) through the MOS gated diode, a plurality of MGDs each with a respective MGD gate electrode (360) in a respective MGD trench (110) is arranged aside each other.
Regarding claim 12, Wutte and Liu together disclose the semiconductor die of claim 11 as applied above, but Wutte fails to explicitly disclose wherein in the vertical cross-section, at least ten MGDs are arranged aside each other.
In the similar field of endeavor of semiconductor devices, Fig. 1 of Liu discloses wherein in the vertical cross-section, at least ten MGDs (126) are arranged aside each other (shown in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wutte with the MGD arrangement as disclosed by Liu, to reduce parasitic inductance and increase switching frequency (see Liu, ¶ [0022-0023]).
Regarding claim 13, Figs. 3 and 4A of Wutte disclose a method of manufacturing a semiconductor die, the method comprising:
forming a vertical transistor device (380) having a gate electrode (360) in a gate trench (“components of the transistors such as the gate electrode are typically disposed in trench structures formed in a main surface of a semiconductor substrate”, ¶ [0002]); and
forming a MOS gated diode (MGD) having an MGD gate electrode (360) in an MGD trench (110),
wherein the gate trench (110) has an elongated extension in a first lateral direction (horizontal direction in Fig. 3) (“forming a first trench”, ¶ [0009]).
Wutte fails to explicitly disclose wherein the vertical transistor device and the MGD are arranged consecutively in the first lateral direction.
In the similar field of endeavor of semiconductor devices, Figs. 1-2 of Liu disclose wherein the vertical transistor device (102) and the MGD (126) are arranged consecutively in the first lateral direction (A-A’ direction in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Wutte with the transistor and MGD arrangement as disclosed by Liu, to reduce parasitic inductance and increase switching frequency (see Liu, ¶ [0022-0023]).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wutte (US 20180226481 A1) and Liu (US 20200168719 A1) in further view of Haeberlen et al. (US 20130228858 A1) herein after “Haeberlen”.
Regarding claim 14, Wutte and Liu together disclose the method of claim 13 as applied above, but Wutte and Liu fail to disclose wherein forming the MGD comprises:
removing a first gate oxide from the MGD trench; and
forming a second gate oxide, which is thinner than the first gate oxide, in the MGD trench.
In the similar field of endeavor of semiconductor devices, Figs. 37-38 of Haeberlen disclose wherein forming the MGD comprises:
removing a first gate oxide (Fig. 37, first insulating portion 12a, ¶ [0086]) from the MGD trench (Fig. 37, trench 20, ¶ [0086]) (“the insulating oxide layer on the sidewalls of the second trench 20 and on the source region 80 adjoining the second trench 20 are removed using an isotropic etching process”, ¶ [0132]); and
forming a second gate oxide (Fig. 38, second insulating portion 22a, ¶ [0086]), which is thinner than the first gate oxide (12a), in the MGD trench (“a thermal oxidation is carried out to form second insulating portion 22a on the side walls in the upper portion of the second trench 20”, “the second insulating portions 22a are… thinner than the first insulating portions 12a”, ¶ [0132]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wutte with the oxide processes as disclosed by Haeberlen, to obtain a device with the desired electric field (see Haeberlen, ¶ [0137]).
Regarding claim 15, Wutte, Liu, and Haeberlen disclose the method of claim 14 as applied above, but Wutte and Liu fail to disclose wherein an etch mask defines an opening for the removing of the first gate oxide, the opening extending across a plurality of trenches in a second lateral direction perpendicular to the first lateral direction.
In the similar field of endeavor of semiconductor devices, Figs. 4 and 41 of Haeberlen disclose wherein an etch mask (Fig. 41, mask 7b, ¶ [0132]) defines an opening for the removing of the first gate oxide (12a), the opening extending across a plurality of trenches (“that it includes two second trenches 20”, ¶ [0084]) in a second lateral direction perpendicular to the first lateral direction (horizontal direction in Fig. 4).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Wutte with the oxide processes as disclosed by Haeberlen, to obtain a device with the desired electric field (see Haeberlen, ¶ [0137]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights