DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application and are currently being examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/9/2025 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0045] refers to gate 406 and first dielectric layer 404. This appears to be a typo meant to be in reference to gate 512 and first dielectric layer 510.
Appropriate correction is required.
The use of the terms Google Android™, Apple OS X™, Linux™, and Wi-Fi™ (not an exhaustive list, paragraphs [0058]-[0059] have numerous instances of trade names), which are a trade name or a mark used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Objections
Claim 18 is objected to because of the following informalities: Line 1 of claim 18 states “a full width across the perimeter of the pixel”. This appears to be a typo meant to say “a full width across the pixel”. Appropriate correction is required. For the purposes of examination, claim 18 will be interpreted to read, “a full width across the pixel”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2010/0181634 A1, hereafter Wang) in view of Cheng et al. (US 2019/0140006 A1, hereafter Cheng).
Regarding claim 1, Wang teaches in Fig. 5, an image sensor (500, [0036]), comprising:
a semiconductor substrate (202, [0011]) having a given thickness (505, [0037]) between a top surface (front side, 204, [0011]) and a bottom surface (back side, (206, [0011]) of the semiconductor substrate (202); and
a plurality of pixels (502A and 502B, similar to 202A and 202B, [0011]) arranged across the substrate (202), wherein a pixel (502A) of the plurality of pixels (502A and 502B) comprises
a first dielectric wall (512, 516, [0036]) extending into the semiconductor substrate (202) at a first distance from the top surface of the semiconductor substrate (204), and
a second dielectric wall (572, 576, [0037]) arranged below the first dielectric wall (512, 516), the second dielectric wall (572, 576) extending into the semiconductor substrate (202) at a second distance from the bottom surface of the semiconductor substrate (206), wherein a sum of the first distance and the second distance is equal to the given thickness of the semiconductor substrate (505).
While Wang is silent on the first and second dielectric walls arranged around a perimeter of the pixel, due to a lack of a top-down view of the pixels, Cheng shows a similar image sensor in Fig. 1E with dielectric walls (160 [0046] and 124 [0025]) similar to those in Wang. Cheng further shows these dielectric walls around the perimeter of the pixel in Figs. 2A and 2B. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric walls of Wang to surround the perimeter of the pixel as shown in Cheng to get the expected result of electrically isolating adjacent devices from one another ([0028] of Cheng).
Regarding claim 2, Wang in view of Cheng teach the image sensor of claim 1. Wang further teaches in Fig. 5, the pixel (502A, [0011]) comprises a first doped substrate portion (226, [0013]) over a second doped substrate portion (286, [0022]), wherein the first doped substrate portion (226) contacts a sidewall of the first dielectric wall (512, 516, [0036]), and wherein the second doped substrate portion (286) contacts a sidewall of the second dielectric wall (572, 576, [0037]).
Examiner’s note, Wang discloses the doped regions can both be up to halfway through the substrate, so for the purposes of examination, the first and second doped portions will meet in the middle, similar to the dielectric walls, see annotated Fig. 5.
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Regarding claim 5, Wang in view of Cheng teach the image sensor of claim 1. Wang further teaches in Fig. 5 the first dielectric wall (512, 516, [0036]) has a first width along the top surface of the semiconductor substrate between 0.3 micrometers and 0.8 micrometers [0036], within the range of 0.3 to 1.0 micrometers, and the second dielectric wall (572, 576, [0037]) has a second width along the bottom surface of the semiconductor substrate between 0.1 micrometers and 0.5 micrometers [0037].
Regarding claim 6, Wang in view of Cheng teach the image sensor of claim 1. Wang further teaches in Fig. 5 the first distance is substantially equal to the second distance. As 512 and 572 are both disclosed as about 1 micrometer, they are substantially equal.
Regarding claim 7, Wang in view of Cheng teach the image sensor of claim 1. Wang in view of Cheng fails to teach the given thickness of the semiconductor substrate is between 10 micrometers and 20 micrometers in Fig. 5 (the thickness 505 of the substrate is described as thinned down and about 2 micrometers). However, Wang teaches the substrate can be variable depending upon the application and design requirements, and can be in a range of 0.5 micrometers to 20 micrometers, completely encapsulating the range of the present application [0017].
Claim(s) 3, 14-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cheng, and further in view of Iida et al. (US 2023/0299113 A1, hereafter Iida).
Regarding claim 3, Wang in view of Cheng teach the image sensor of claim 2. Wang further teaches the first doped substrate portion (226, [0013]) includes n-type dopants (Wang teaches 226 is doped with phosphorous, a known n-type dopant [0013]).
Wang fails to teach the second doped substrate portion includes p-type dopants (Wang teaches 286 is doped with a same type dopant as 226). However, Wang teaches a p-type dopant (boron) can be used to make a p-type region in [0013]. Wang fails to teach 226 and 286 to have opposite polarity.
However, Iida teaches a CMOS imaging device in Fig. 5 in which a p-n junction is formed between doped regions 91a2 and 91a2 [0070]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second doped substrate portion of Wang in view of Cheng to include p-type dopants (boron according to Wang) to form a p-n junction between the first and second doped substrate portions in order to reduce dark current in the device, as Iida states in [0070].
Regarding claim 14, in Fig. 5 Wang teaches a pixel of a pixel array within a CMOS image sensor, the pixel comprising:
a first semiconductor region (226, [0013]) having n-type dopants (Wang teaches 226 is doped with phosphorous, a known n-type dopant [0013]);
a second semiconductor region (286, [0022]) beneath the first semiconductor region (286);
a first dielectric wall (512, 516, [0036]) extending through a thickness of the first semiconductor region (286); and
a second dielectric wall (572, 576, [0037]) extending through a thickness of the second semiconductor region (286), wherein the second dielectric wall (572, 576) contacts the first dielectric wall (512, 516).
While Wang is silent on the first and second dielectric walls arranged around a perimeter of the pixel, due to a lack of a top-down view of the pixels, Cheng shows a similar image sensor in Fig. 1E with dielectric walls (160 [0046] and 124 [0025]) similar to those in Wang. Cheng further shows these dielectric walls around the perimeter of the pixel in Figs. 2A and 2B. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric walls of Wang to surround the perimeter of the pixel as shown in Cheng to get the expected result of electrically isolating adjacent devices from one another ([0028] of Cheng).
Wang in view of Cheng fails to teach the second semiconductor region having a second concentration of p-type dopants(Wang teaches 286 is doped with a same type dopant as 226). However, Wang teaches a p-type dopant (boron) can be used to make a p-type region in [0013]. Wang fails to teach 226 and 286 to have opposite polarity.
However, Iida teaches a CMOS imaging device in Fig. 5 in which a p-n junction is formed between doped regions 91a2 and 91a2 [0070]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second doped substrate portion of Wang in view of Cheng to include p-type dopants (boron according to Wang) to form a p-n junction between the first and second doped substrate portions in order to reduce dark current in the device, as Iida states in [0070].
Examiner’s note, Wang discloses the doped regions can both be up to halfway through the substrate, so for the purposes of examination, the first and second doped portions will meet in the middle, similar to the dielectric walls, see annotated Fig. 5.
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Regarding claim 15, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. Wang further teaches in Fig. 5 the first distance is substantially equal to the second distance. As 512 and 572 are both disclosed as about 1 micrometer, they are substantially equal.
Regarding claim 16, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. Wang in view of Cheng fails to teach the given thickness of the semiconductor substrate is between 10 micrometers and 20 micrometers in Fig. 5 (the thickness 505 of the substrate is described as thinned down and about 2 micrometers). However, Wang teaches the substrate can be variable depending upon the application and design requirements, and can be in a range of 0.5 micrometers to 20 micrometers, completely encapsulating the range of the present application [0017].
Regarding claim 17, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. While Wang in view of Cheng in view of Iida do not explicitly teach a boundary between the first semiconductor region (226, [0013]) and the second semiconductor region (286, [0022]) is within 200 nm above and 200 nm below a boundary between the first dielectric wall (512, 516, [0036]) and the second dielectric wall (572, 576, [0037]), Wang does disclose a depth of the first semiconductor region (226) to be between 0.2 micrometers to 1.5 micrometers [0013] and the second semiconductor region (286) to be between 0.5 micrometers to 2.5 micrometers [0022], and the depth of the first dielectric wall (512, 516) and the second dielectric wall (572, 576) ) to be between 0.5 micrometers to 2 micrometers [0036]-[0037]. These ranges would allow for a boundary between the first semiconductor region (226) and the second semiconductor region (286) to be within 200 nm above and 200 nm below a boundary between the first dielectric wall (512, 516) and the second dielectric wall (572, 576) under the provided parameters.
Regarding claim 19, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. Wang further teaches in Fig. 5 the first dielectric wall (512, 516, [0036]) has a largest width between 0.3 micrometers and 0.8 micrometers [0036], within the range of 0.3 to 1.0 micrometers, and the second dielectric wall (572, 576, [0037]) has a largest width between 0.1 micrometers and 0.5 micrometers [0037].
Regarding claim 20, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. Wang further teaches in Fig. 5 a top surface of the second dielectric wall (572, 576, [0037]) contacts a bottom surface of the first dielectric wall (512, 516, [0036]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cheng, and further in view of Iida and in view of Kao et al. (US 2013/0320420 A1, hereafter Kao).
Regarding claim 4, Wang in view of Cheng teach the image sensor of claim 2, wherein the first doped substrate portion (226, [0013]) has a concentration of n-type dopants (Wang teaches 226 is doped with phosphorous, a known n-type dopant [0013]).
Wang in view of Cheng fail to teach the second doped substrate portion has a concentration of p-type dopants (Wang teaches 286 is doped with a same type dopant as 226). However, Wang teaches a p-type dopant (boron) can be used to make a p-type region in [0013]. Wang fails to teach 226 and 286 to have opposite polarity.
However, Iida teaches a CMOS imaging device in Fig. 5 in which a p-n junction is formed between doped regions 91a2 and 91a2 [0070]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second doped substrate portion of Wang in view of Cheng to include p-type dopants (boron according to Wang) to form a p-n junction between the first and second doped substrate portions in order to reduce dark current in the device, as Iida states in [0070].
Wang in view of Cheng in view of Iida are silent on the concentration of n-type dopants between about 1x1013 and 1x1014 cm-3 and the concentration of p-type dopants being between about 1x1015 and 1x1016 cm-3. However, one of ordinary skill in the art would know to use doping concentrations known in the art before the effective filing date. Kao teaches an image sensor with a p-type region (24, [0008]) and an n-type region (46, [0013]). The p-type region can have a concentration of 1x1015 to 1x1016 cm-3 [0008] and the n-type region can have a concentration of 1x1013 and 1x1014 cm-3 [0013]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second doped substrate regions to have the concentrations of dopants as taught by Kao in order to get a functioning device.
Claim(s) 8-9 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2023/0131477 A1) in view of Wang and in view of Cheng.
Regarding claim 8, Sato teaches in Fig. 2 an image sensor (image capturing device, 102, [0025]), comprising:
a pixel array (pixel section, 203, [0030]) having at least one column of addressable pixels (see annotated Fig. 2. Sato describes the signals being read from an upper row to a lower row, implying columns [0030]);
a column amplifier (204, [0033]) coupled to the at least one column of addressable pixels;
an analog-to-digital converter (ADC) (205, [0033]) coupled to the column amplifier (204); and
a processor (207, [0035]) coupled to the ADC (205);
wherein the at least one column of addressable pixels includes a pixel (see annotated Fig. 2).
Sato is silent on a pixel that comprises
a first dielectric wall arranged around a perimeter of the pixel and extending into a semiconductor substrate at a first distance from a top surface of the semiconductor substrate, and
a second dielectric wall arranged around the perimeter of the pixel and below the first dielectric wall, the second dielectric wall extending into the semiconductor substrate at a second distance from a bottom surface of the semiconductor substrate, wherein a top surface of the second dielectric wall contacts a bottom surface of the first dielectric wall.
However, Wang teaches in Fig. 5 a pixel (502A, [0011]) of the plurality of pixels (502A and 502B, [0011], similar to the column of pixels in Mun) comprises
a first dielectric wall (512, 516, [0036]) extending into the semiconductor substrate (202, [0011]) at a first distance from the top surface of the semiconductor substrate (204, [0011]), and
a second dielectric wall (572, 576, [0037]) arranged below the first dielectric wall (512, 516), the second dielectric wall (572, 576) extending into the semiconductor substrate (202) at a second distance from the bottom surface of the semiconductor substrate (206, [0011]), wherein a sum of the first distance and the second distance is equal to the given thickness of the semiconductor substrate (505, [0037]).
While Wang is silent on the first and second dielectric walls arranged around a perimeter of the pixel, due to a lack of a top-down view of the pixels, Cheng shows a similar image sensor in Fig. 1E with dielectric walls (160 [0046] and 124 [0025]) similar to those in Wang. Cheng further shows these dielectric walls around the perimeter of the pixel in Figs. 2A and 2B. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric walls of Wang to surround the perimeter of the pixel as shown in Cheng to get the expected result of electrically isolating adjacent devices from one another ([0028] of Cheng).
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Regarding claim 9, Sato in view of Wang in view of Cheng teach the image sensor of claim 8. Wang further teaches in Fig. 5, the pixel (502A, [0011]) comprises a first doped substrate portion (226, [0013]) over a second doped substrate portion (286, [0022]), wherein the first doped substrate portion (226) contacts a sidewall of the first dielectric wall (512, 516, [0036]), and wherein the second doped substrate portion (286) contacts a sidewall of the second dielectric wall (572, 576, [0037]).
Examiner’s note, Wang discloses the doped regions can both be up to halfway through the substrate, so for the purposes of examination, the first and second doped portions will meet in the middle, similar to the dielectric walls, see annotated Fig. 5.
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Regarding claim 12, Sato in view of Wang in view of Cheng teach the image sensor of claim 8. Wang further teaches in Fig. 5 the first distance is substantially equal to the second distance. As 512 and 572 are both disclosed as about 1 micrometer, they are substantially equal.
Regarding claim 13, Wang in view of Cheng teach the image sensor of claim 8. Sato in view of Wang in view of Cheng fails to teach the given thickness of the semiconductor substrate is between 10 micrometers and 20 micrometers in Fig. 5 (the thickness 505 of the substrate is described as thinned down and about 2 micrometers). However, Wang teaches the substrate can be variable depending upon the application and design requirements, and can be in a range of 0.5 micrometers to 20 micrometers, completely encapsulating the range of the present application [0017].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Wang in view of Cheng, and further in view of Iida.
Regarding claim 10, Sato in view of Wang in view of Cheng teach the image sensor of claim 9. Wang further teaches the first doped substrate portion (226, [0013]) includes n-type dopants (Wang teaches 226 is doped with phosphorous, a known n-type dopant [0013]).
Wang fails to teach the second doped substrate portion includes p-type dopants (Wang teaches 286 is doped with a same type dopant as 226). However, Wang teaches a p-type dopant (boron) can be used to make a p-type region in [0013]. Wang fails to teach 226 and 286 to have opposite polarity.
However, Iida teaches a CMOS imaging device in Fig. 5 in which a p-n junction is formed between doped regions 91a2 and 91a2 [0070]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second doped substrate portion of Wang in view of Cheng to include p-type dopants (boron according to Wang) to form a p-n junction between the first and second doped substrate portions in order to reduce dark current in the device, as Iida states in [0070].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Wang in view of Cheng in view of Iida and in view of Kao.
Regarding claim 11, Sato in view of Wang in view of Cheng teach the image sensor of claim 9, wherein the first doped substrate portion (226, [0013]) has a concentration of n-type dopants (Wang teaches 226 is doped with phosphorous, a known n-type dopant [0013]).
Sato in view of Wang in view of Cheng fail to teach the second doped substrate portion has a concentration of p-type dopants (Wang teaches 286 is doped with a same type dopant as 226). However, Wang teaches a p-type dopant (boron) can be used to make a p-type region in [0013]. Wang fails to teach 226 and 286 to have opposite polarity.
However, Iida teaches a CMOS imaging device in Fig. 5 in which a p-n junction is formed between doped regions 91a2 and 91a2 [0070]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the second doped substrate portion of Wang in view of Cheng to include p-type dopants (boron according to Wang) to form a p-n junction between the first and second doped substrate portions in order to reduce dark current in the device, as Iida states in [0070].
Sato in view of Wang in view of Cheng in view of Iida are silent on the concentration of n-type dopants between about 1x1013 and 1x1014 cm-3 and the concentration of p-type dopants being between about 1x1015 and 1x1016 cm-3. However, one of ordinary skill in the art would know to use doping concentrations known in the art before the effective filing date. Kao teaches an image sensor with a p-type region (24, [0008]) and an n-type region (46, [0013]). The p-type region can have a concentration of 1x1015 to 1x1016 cm-3 [0008] and the n-type region can have a concentration of 1x1013 and 1x1014 cm-3 [0013]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second doped substrate regions to have the concentrations of dopants as taught by Kao in order to get a functioning device.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Cheng in view of Iida, and further in view of Street et al. (US 2003/0127647 A1, hereafter Street).
Regarding claim 18, Wang in view of Cheng in view of Iida teach the image sensor of claim 14. Wang in view of Cheng in view of Iida fail to teach a full width across the perimeter of the pixel is between about 8 micrometers and about 12 micrometers. However, Street teaches in Fig. 2(A) a CMOS image sensor in which the pixels have a width of 5-15 micrometers, which includes 8-12 micrometers [0029]. While Wang teaches a maximum pixel width of 5.8 micrometers (taking the width of 516 being up to 0.8 microns [0036], only one length necessary as it is shared between pixels, and the width of 226 being up to 5 microns [0013]), one of ordinary skill in the art would be motivated to use a larger pixel as for the expected result of a larger light capturing area.
Conclusion
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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