DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Drawings 3
IV. Claim Rejections - 35 USC § 102 4
A. Claims 11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0379782 (“Hsu”). 4
B. Claims 11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0290864 (“Ho”). 7
V. Allowable Subject Matter 9
VI. Pertinent Prior Art 11
Conclusion 12
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of invention group II, claims 11-20, in the reply filed on 06/16/2026 is acknowledged.
III. Drawings
The drawings are objected to because they fail to comply with 37 CFR 1.84(p)(3) which requires the minimum size of the text for reference characters be a minimum of 1/8th inch. Currently, the text size is about 1/16th inch. In addition, at least reference characters 702 and 704 are illegible as they are black text on dark grey background.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
IV. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0379782 (“Hsu”).
With regard to claim 11, Hsu discloses,
11. A method comprising:
[1] forming a set of trenches 250 in a semiconductor structure 204/205 [¶¶ 14-16, 25; Figs. 5C, 6C];
[2] forming a first inner spacer [e.g. 255 on left sidewall of 210' on either gate stack 240 in Fig. 6C] and a second inner spacer [e.g. 255 on right sidewall of 210' on either gate stack 240 in Fig. 6C] in the set of trenches 250 [¶ 25];
[3a] forming a third inner spacer [e.g. 255 on left sidewall of 210 directly above 210' on either gate stack 240 in Fig. 6C] and a fourth inner spacer [e.g. 255 on right sidewall of 210 directly above 210' on either gate stack 240 in Fig. 6C] in the set of trenches 250 [¶ 25],
[3b] wherein the third inner spacer is disposed on the first inner spacer [as shown in Fig. 6C], and
[3c] wherein the fourth inner spacer is disposed on the second inner spacer [as shown in Fig. 6C]; and
[6a] forming a backside source/drain contact 282 in the set of trenches 250 [¶¶ 45-48; Figs. 19B and 20A-20B],
[6b] wherein an upper surface of the backside source/drain contact 282 is disposed above a bottom surface of the first inner spacer or the second inner spacer [see explanation below and annotated Fig. 20B], and
[6c] wherein the upper surface of the backside source/drain contact 282 is disposed below an upper surface of the third inner spacer or the fourth inner spacer [see explanation below and annotated Fig. 20B].
NOTE: Hsu shows the backside as the upper surface in Figs. 19B and 20A-20B, as explicitly stated in Fig. 20A. Features [6b] and [6c] of claim 11 have been interpreted by rotating Fig. 20B of Hsu by 180° in the plane of the page so that the backside becomes the lower surface, as consistent with the configuration of Figs. 1A-1C of the Instant Application, showing the backside as the lower surface. In addition, Fig. 20 of Hsu has been reproduced below, inverted and with annotations showing the inner spacers 255 relative to the backside source/drain contact 282.
As shown, the upper (curved) surface of 282 is (1) above the bottom surfaces of the first and second inner spacers 255, as required by feature [6b] and (2) below the upper surfaces of the third and fourth inner spacers 255, as required by feature [6c].
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678
630
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(Annotated version of Fig. 20B of Hsu)
This is all of the limitations of claim 11.
With regard to claim 15, Hsu further discloses,
15. The method of claim 11, further comprising:
[1] depositing a high-k 349 metal 340/350 gate material between the first inner spacer and the second inner spacer 255 [¶ 36; labeled in Fig. 13D and shown but not labeled in Fig. 20B]; and
[2] depositing the high-k metal gate material between the third inner spacer and the fourth inner spacer 255 [¶ 36; labeled in Fig. 13D and shown but not labeled in Fig. 20B].
B. Claims 11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0290864 (“Ho”).
With regard to claim 11, Ho discloses, generally in Figs. 17 through 24A,
11. A method comprising:
[1] forming a set of trenches 46A, 46B in a semiconductor structure 12/12'/22' [¶¶ 70, 73-74, 80; Figs. 18, 22];
[2] forming a first inner spacer [142A in Figs. 19-20 (¶¶ 75-77)] and a second inner spacer [142B in Figs. 21-23 (¶¶ 75-77)] in the set of trenches 46A, 46B [¶ ;
[3a] forming a third inner spacer [54 contacting 142A] and a fourth inner spacer [54 contacting 142B] in the set of trenches 46A, 46B,
[3b] wherein the third inner spacer [142B in Figs. 21-23 (¶¶ 75-77)] is disposed on the first inner spacer [142A in Figs. 19-20 (¶¶ 75-77)], and
[3c] wherein the fourth inner spacer [54 contacting 142B] is disposed on the second inner spacer [142B in Figs. 21-23 (¶¶ 75-77)]; and
[6a] forming a backside source/drain contact 134 in the set of trenches 46A, 46B [¶¶ 64, 85],
[6b] wherein an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer [142A in Figs. 19-20 (¶¶ 75-77)] or the second inner spacer [142B in Figs. 21-23 (¶¶ 75-77)], and
[6c] wherein the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer [142A in Figs. 19-20 (¶¶ 75-77)] or the fourth inner spacer [54 contacting 142B].
NOTE: Ho shows the backside as the upper surface in Figs. 24A. Features [6b] and [6c] of claim 11 have been interpreted by rotating Fig. 24A of Ho by 180° in the plane of the page so that the backside becomes the lower surface, as consistent with the configuration of Figs. 1A-1C of the Instant Application, showing the backside as the lower surface. In addition, Fig. 24A of Ho has been reproduced below, inverted and with annotations showing the inner spacers 142A, 142B, 54 relative to the backside source/drain contact 134. Note, in addition, that the structure assigned reference character 16' in Fig. 24A is composed of 142A and 142B (Ho: ¶ 83)
As shown, the upper surface of 134 is (1) above the bottom surfaces of the first and second inner spacers 16'(142A/142B), as required by feature [6b] and (2) below the upper surfaces of the third and fourth inner spacers 54, as required by feature [6c].
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543
692
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(Annotated version of Fig. 24A of Ho)
This is all of the limitations of claim 11.
With regard to claim 15, Ho further discloses,
15. The method of claim 11, further comprising:
[1] depositing a high-k [78 (¶ 46)] metal [80L (¶¶ 47-48)] gate material between the first inner spacer [142A in Figs. 19-20 (¶¶ 75-77)] and the second inner spacer [142B in Figs. 21-23 (¶¶ 75-77)]; and
[2] depositing the high-k [78 (¶ 46)] metal [80L (¶¶ 47-48)] gate material between the third inner spacer 54 and the fourth inner spacer 54.
V. Allowable Subject Matter
Claims 12-14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 12 reads,
12. The method of claim 11, wherein the semiconductor structure includes:
[1] a silicon substrate;
[2] a first sacrificial layer disposed on the silicon substrate, wherein the first sacrificial layer includes SiGe25%;
[3] a silicon layer disposed on the first sacrificial layer;
[4] a silicon etch stop layer disposed on the silicon layer, wherein the silicon etch stop includes SiGe55%;
[5] a second sacrificial layer disposed on the silicon etch stop;
[6] a first nanosheet layer disposed on the second sacrificial layer;
[7] a third sacrificial layer disposed on the first nanosheet layer;
[8] a second nanosheet layer disposed on the third sacrificial layer;
[9] a fourth sacrificial layer disposed on the second nanosheet layer; and
[10] a third nanosheet layer disposed on the fourth sacrificial layer.
With regard to claim 12, Hsu further discloses,
12. The method of claim 11, wherein the semiconductor structure includes:
[1] a silicon substrate 202 [¶ 14: “carrier 202 may be part of a silicon wafer”];
[2] a first sacrificial layer 203 disposed on the silicon substrate 202, wherein the first sacrificial layer includes … [an insulator, e.g. SiO2 (¶ 14)];
[3] a silicon layer 204 disposed on the first sacrificial layer 203 [¶ 14: “the semiconductor layer 204 can be silicon”];
[4] … [not taught] …
[5] … [not taught] …
[6] a first nanosheet layer 215 disposed on the second sacrificial layer;
[7] a third sacrificial layer 210 disposed on the first nanosheet layer;
[8] a second nanosheet layer 215 disposed on the third sacrificial layer;
[9] a fourth sacrificial layer 210 disposed on the second nanosheet layer; and
[10] a third nanosheet layer 215 disposed on the fourth sacrificial layer.
Hsu does not disclose that the first sacrificial layer 203 is SiGe 25% as required by feature [2] or either of features [4] and [5].
With regard to claim 12, Ho further discloses, generally in Fig. 18,
12. The method of claim 11, wherein the semiconductor structure includes:
[1] a silicon substrate 12 [¶¶ 70, 17];
[2] … [not taught] …
[3] … [not taught] …
[4] a silicon etch stop layer 24B disposed on the silicon …[substrate 12]…, wherein the silicon etch stop includes SiGe55% [¶ 71; ¶ 35: “In some embodiments where the dummy nanostructures 24B are formed of germanium or silicon germanium with a high germanium atomic percentage, …”];
[5] a second sacrificial layer 24A disposed on the silicon etch stop 24B;
[6] a first nanosheet layer 26L disposed on the second sacrificial layer 24A;
[7] a third sacrificial layer 24A disposed on the first nanosheet layer 26L;
[8] a second nanosheet layer 26L disposed on the third sacrificial layer 24A;
[9] a fourth sacrificial layer 24A disposed on the second nanosheet layer 26L; and
[10] a third nanosheet layer 26L disposed on the fourth sacrificial layer 24A.
Thus, Ho does not disclose the layers of the substrate required by features [2] ad [3].
In the context of the process, the prior art does not reasonably teach or suggest—in the context of the claims—the semiconductor structure including the limitations recited in features [2], [4], or [5] or in [2] or [3].
Claims 13, 14, and 16-20 would be allowable for including the same allowable limitations by depending from claim 12, either directly or indirectly.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0212455 (“Liu”) is cited for disclosing at least all of the limitations of claim 11 for similar reasons to those explained above in the rejection over Hsu. See Figs. 24-27 and associated text.
US 2025/0194154 (“Qin”) is cited for disclosing at least all of the limitations of claim 11. See at least Figs. 10A-10C through 12A-12C for the first through fourth inner spacer formation and Figs. 14A-14C through 17A-17C for the backside source/drain contact, as well as the associated text.
US 2021/0043727 (“Frougier”) is cited for disclosing a process of forming vertically- stacked, directly-contacting inner spacer pairs, e.g. 121(=141/142a). See Figs. 1A, 2A, and 3, for structural variations and Figs. 4 through 19 for the process, as associated text. However, no backside source/drain contact is formed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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