DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2015/0347665 to Sapatnekar et al. (“Sapatnekar”) in view of US Pub. No. 2012/0017188 to Lepak et al. (“Lepak”), and in further view of US Pub. No. 2006/0146759 to Guo et al. (“Guo”).
As to independent claim 1 and similarly recited independent claims 11 and 18, a computer-implemented method (¶ 0005), a computer-readable storage media (Fig. 7: 18, 18, 40. For purposes of examination, the phrase “computer-readable storage media” in claim 11 is construed consistent with ¶ 0031 of the Specification as referring to non-transitory storage media. ¶ 0031 explains the disclosed storage media are storage mediums included in tangible storage devices and expressly states a computer-readable storage medium, as used in the Specification, is not to be construed as storage in the form of transitory signals per se. Accordingly, the prior art rejections of claim 11 is based on computer-readable storage media that are non-transitory.), a system (Fig. 7: 10, 18, 20, 12) comprising: performing, by at least one processor set, signal electromigration analysis on a logic circuit design for an integrated circuit (¶ 0048, 0050. Sapatnekar teaches a processor implement signal electromigration analysis performed on a logic/IC circuit design including cells, a netlist, interconnects, and design constraints.), the performing comprising: producing a (¶ 0048, 0049. Sapatnekar teaches generating a matrix of electrical current values from SPICE simulations of circuit output transitions under different input slew/output load conditions, but does not teach generating a state analysis based transition matrix from state analysis data.); (¶ 0051, 0052. Sapatnekar teaches weighting current values obtained from multiple SPICE characterization conditions and using switching probability/activity information to scale simulation derived currents for EM analysis, but does not teach determining those simulation weighs from transition submatrices together with switching factor data.); applying the determined per simulation weighting factors to weight, for signal electromigration analysis, electrical current data collected from a plurality of timing simulations of a transient simulator for the logic circuit design (¶ 0049, 0052. Sapatnekar teaches obtaining electrical current data from multiple SPICE simulations of output transitions behavior under different timing related slew/load conditions and applying weighting when combining those simulation derived current values.); using the weighted electrical current data in assessing signal electromigration impact on circuit performance of the logic circuit design (¶ 0069-0072. Sapatnekar teaches using simulation derived and activity adjusted electrical current information to calculate Joule heating and electromigration Time-to-Failure, thereby assessing EM impact on circuit lifetime/performance.); and based on the assessing of the impact on circuit performance, facilitating generating a modified logic circuit design through modifying of the logic circuit design (¶ 0073-0075. Sapatnekar teaches modifying the IC design based on the EM assessment by constraining unacceptable pin locations, regenerating placement/interconnect routing, and modifying cell structures to reduce electromigration susceptibility.).
Sapatnekar therefore teaches the overall claimed environment and downstream processing. Specifically, transient circuit simulations producing electrical current data, weighting/adjusting those currents based on operating conditions and switching activity, using the resulting currents for signal electromigration assessment, and modifying the circuit design based on that assessment.
Sapatnekar does not, however, teach the particular mechanism by which claim 1 determines the simulation weights. More particularly, Sapatnekar does not teach: producing a state-analysis-based transition matrix using state-analysis data for the logic circuit design, partitioning that state-analysis-based transition matrix into transition submatrices, and determining the per simulation weighting factors using the transition submatrices and switching factor data.
Lepak teaches obtaining logic transition activity data from simulation of an IC design and mathematically solving for corresponding contribution weights from those activity factors, and further teaches reducing the complexity of that weighting problem by constraining/blocking the problem and automatically extracting timing/activity information and solving the weighting equations (¶ 0025-0028, 0040, claim 5).
Guo teaches representing transitions from one state to another using a state-transition matrix and partitioning the state-transition matrix into blocks/submatrices, with the partitioning used to reduce the computational burden associated with large matrix operations (claim 8, ¶ 0011, 0026, 0027, 0033, 0034, 0044-0046).
It would have been obvious to a PHOSITA to modify Sapatnekar’s simulation-based signal electromigration analysis according to Lepak’s activity derived weighting technique and Guo’s state-transition matrix partitioning technique.
The modification involves: retaining Sapatenkar’s transient simulations and associated current values; using switching/activity information associated with the simulated circuit transitions, as taught by Lepak, to formulate the weighting relationship; represent the relevant transition relationships with a state-transition matrix and partition that matrix into block/submatrices, as taught by Gau; apply Lepak’s activity factor based weight solving technique to the partitioned transition matrix block/submatrices produced according to Guo, thereby determining respective contribution weights from switching/activity data using the partitioned transition information; and, as taught by Sapatnekar, apply the resulting weights to the corresponding simulation derived electrical current contributions and thereafter use the weighed/adjusted current information for EM assessment and circuit design modification.
Using Guo’s partitioned transition matrix organization when implementing Lepak’s activity derived weighting in Sapatnekar would have been a predictable use of known techniques to obtain their established computation benefits, e.g., reducing computational burden.
Claims 2, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sapatnekar, Lepak, and Guo and in further view of US Pub. No. 2013/0167098 to Fennell et al. (“Fennell”).
The combination of Sapatnekar, Lepak, and Guo does not teach the limitation of claim 2.
Fennell is directed to systems and methods for EDA (¶ 0001). Fennell teaches output specific decomposition of circuit transition information by defining each logic cone as logic having multiple inputs feeding a single output, separately processing the respective logic cones, and splitting the circuit design into such individual cones, and associating the relevant state transition information with the corresponding cone output (¶ 0035, 0053-0055, 0059).
It would have been obvious to a PHOSITA to apply Fennell’s known single output decomposition to the transition matrix partitioning taught by the Sapatnekar/Lepak/Guo combination, such that the transition information associated with each respective circuit output is placed in a corresponding transition submatrix, thereby defining the transition submatrices per output of the logic circuit design. Fennell expressly teaches separately processing single output logic cones to permit independent processing, improve scalability, and reduce computational effort (¶ 0053-0055). Applying that known output based organization to Guo’s already partitioned transition information would have been a predictable use of a known circuit partitioning technique according to its established function, with the predictable result that each transition submatrix corresponds to a respective output.
Claims 3, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sapatnekar, Lepak, and Guo and in further view of US Pub. No. 2003/0121013 to Moon et al. (“Moon”).
The combination of Sapatnekar, Lepak, and Guo does not teach the limitation of claim 3.
Moon is directed to the field of timing model extraction (¶ 0003). Moon teaches organizing circuit transition information on a per timing arc basis by providing a timing graph having individual delay arcs and associating a respective transition matrix with each delay arc, the respective matrix defining the valid transitions between that arc’s source and sink pins; Moon specifically illustrates a transition matrix associated with a CLK [Wingdings font/0xE0] Q delay arc (¶ 0036, Fig. 2B).
It would have been obvious to a PHOSITA to apply Moon’s known per timing arc transition organization to the transition matrix partitioning taught by the Sapatnekar/Lepak/Guo combination, such that the entries pertaining to a respective timing arc are grouped into a corresponding transition submatrix, thereby defining the transition submatrices per timing arc of the logic circuit design.
Moon demonstrates transition behavior may be represented separately for each timing arc because the valid interest are the transitions between that particular arc’s source and sink pins (¶ 0036). The PHOSITA would have been motivated to use the individual timing arcs as the partition boundaries for Guo’s transition submatrices so that each resulting submatrix preserves and represents the transition relationships applicable to its corresponding timing arc. This would have amounted to applying Moon’s known arc specific organization to Guo’s known matrix partitioning technique to obtain the predictable result of per timing arc transition submatrices.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sapatnekar, Lepak, and Guo and in further view of US Patent No. 8,516,420 to Kariat et al. (“Kariat”).
The combination of Sapatnekar, Lepak, and Guo does not teach the limitation of claim 10.
Kariat is directed to STA analysis software tool and signal integrity analysis software tools for designing ICs (1:8-11). Kariat teaches a transistor level static timing context in which STA engine operates on channel connected components comprising transistors and employs a current source model that generates and uses transistor level output current/current waveform information in performing electrical and timing calculations (Kariat: 3:5-46, 4:1-30, 5:30-67, 6:1-64, 9:1-6, 33-55).
It would have been obvious to a PHOSITA to implement the current based signal electromigration assessment of Sapatnekar, as modified by Lepak and Guo, within the transistor level static framework taught by Kariat. Kariat teaches that its CCC current source model incorporates transistor derived current waveform information into STA and provides accurate electrical/timing calculations for circuit design analysis. The PHOSITA therefore would have had reason to employ Kariat’s known transistor level current based static timing framework when performing Sapatnekar’s current based electromigration analysis to use the same transistor level electrical characterization and current information for circuit timing and reliability analysis, thereby obtaining accurate circuit level analysis while avoiding redundant electrical characterization. The modification would amount to using a known transistor level STA framework for its established purpose of analyzing transistor derived electrical behavior of an IC design.
Allowable Subject Matter
Claims 4-9 and 14-17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4-9 and 14-17 would be allowable if amended in the manner above because the prior art of record does not teach or suggest a method or CRM having all the combinations of steps or elements as required by and recited in claims 4, 9, or 14. Claims 5-8 and 15-17 depend from claims 4 and 14, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
