Attorney Docket Number: 067237-2349
Filing Date: 2/12/2024
Claimed Foreign Priority Date: 3/16/2023 (JP2023-042393)
Inventors: Hoshi et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 2/12/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Objections
Claim 1 is objected to because of the following informalities: “…arranged at an another end portion of the arrangement of the plurality of first row electrodes…” is improper. For the purposes of examination, “…arranged at an another end portion of the arrangement of the plurality of first row electrodes…” will be construed to recite “…arranged at another end portion of the arrangement of the plurality of first row electrodes…”. Appropriate correction is required.
Claim 4 is objected to because of the following informalities: “…arranged far away from the first side than the plurality of first row electrodes…” is improper. For the purposes of examination, “…arranged far away from the first side than the plurality of first row electrodes…” will be construed to recite “…arranged farther away from the first side than the plurality of first row electrodes…”. Appropriate correction is required.
Claim 7 is objected to because of the following informalities: “…arranged in the first direction and arranged far away from the semiconductor chip than the plurality of first row terminals…” is improper. For the purposes of examination, “…arranged in the first direction and arranged far away from the semiconductor chip than the plurality of first row terminals…” will be construed to recite “…arranged in the first direction and arranged farther away from the semiconductor chip than the plurality of first row terminals…”. Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the fourth wire crossing any ones of the plurality of second row electrodes must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yagyu (US 10128130 B2) in view of Suwa (JP 2006319237 A) further in view of Ishida (US 20140291826 A1).
Regarding claim 1, Yagyu (see, e.g., figs. 1-3C), shows most aspects of the instant invention including a semiconductor device comprising:
A die pad (e.g., die pad DP) having:
A first surface (e.g., top surface of die pad DP), and a plurality of terminals (e.g., plurality of leads (external terminals) LE) arranged over the first surface (e.g., top surface of die pad DP);
A semiconductor chip (e.g., semiconductor chip SC) having: a second surface (e.g., lower surface facing die pad) facing the first surface (e.g., top surface of die pad DP); a third surface (e.g., electrode-comprising surface of semiconductor chip SC) opposite the second surface, and a plurality of electrodes (e.g., plurality of electrode pads BP + paragraph 36) arranged on the third surface (e.g., electrode-comprising surface of semiconductor chip SC), the semiconductor chip (e.g., semiconductor chip SC) being mounted on the die pad (e.g., die pad DP);
A plurality of wires (e.g., bonding wires BW) electrically connecting the plurality of electrodes (e.g., plurality of electrode pads BP + paragraph 36) and the plurality of terminals (e.g., plurality of leads (external terminals) LE);
A sealing body (e.g., sealing body RE) sealing the semiconductor chip (e.g., semiconductor chip SC), the plurality of wires (e.g., bonding wires BW)
Wherein the plurality of electrodes (e.g., plurality of electrode pads BP + paragraph 36) includes a plurality of first row electrodes (see, e.g., annotated fig. 1 below) arranged along a first side (e.g., first side S1) of the third surface (e.g., electrode-comprising surface of semiconductor chip SC); wherein the plurality of first row electrodes (see, e.g., annotated fig. 1 below) includes:
A first end portion electrode (e.g., left-most electrode of electrode row of annotated fig. 1) arranged at a one end portion of an arrangement of the plurality of first row electrodes (see, e.g., annotated fig. 1 below);
A second end portion electrode (e.g., right-most electrode of electrode row of annotated fig. 1) arranged at another end portion of the arrangement of the plurality of first row electrodes (e.g., right-side electrode of annotated fig. 1);
A first non-end portion electrode (e.g., first non-end portion electrode of annotated fig. 1);
Wherein the plurality of terminals (e.g., plurality of leads (external terminals) LE) includes:
A first terminal (e.g., left-side terminal of annotated fig. 1);
A second terminal (e.g., center terminal of annotated fig. 1);
Wherein the plurality of wires (e.g., bonding wires BW) includes:
A first wire (e.g., left-side wire of annotated fig. 1) connected to each of the first end portion electrode (e.g., left-most electrode of electrode row of annotated fig. 1) and the first terminal (e.g., left-side terminal of fig. 2); and
A second wire (e.g., center wire attached to first non-end portion electrode of annotated fig. 1) connected to each of the first non-end portion electrode (e.g., first non-end portion electrode of annotated fig. 1) and the second terminal (e.g., right-side terminal of fig. 2);
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Annotated Fig. 1
Yagyu (see, e.g., figs. 1-3C), however fails to explicitly show a wiring substrate having a first surface and the plurality of terminals is arranged on the first surface, while it also fails to show wherein a loop height of the first wire is greater than a loop height of the second wire.
Suwa (see, e.g., fig. 1), in a similar device to Yagyu, teaches a wiring substrate (e.g., two-layer packaging substrate 2) having a first surface (e.g., top surface of two-layer packaging substrate 2) and a plurality of terminals (e.g., conductive portion 9) is arranged on the first surface (e.g., top surface of two-layer packaging substrate 2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the wiring substrate and directly arranged terminal configuration of Suwa within the device and underneath the semiconductor chip of Yagyu, in order to achieve the expected result of providing a structural and electrical platform beneath the semiconductor chip and terminals as desired.
Yagyu in view of Suwa, however, fails to teach wherein a loop height of the first wire than a loop height of the second wire.
Ishida (see, e.g., fig. 3), in a similar device to Yagyu in view of Suwa, teaches wherein a loop height (e.g., loop height of third wire 4c) of a first wire (e.g., third wire 4c) is greater than a loop height (e.g., loop height of second wire 4b) of a second wire (e.g., second wire 4b).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the differing higher and lower loop heights of Ishida within the first and second wire of Yagyu in view of Suwa respectively, in order to improve electrical reliability within the device and reduced defects within the device (see, e.g., paragraphs 144 of Ishida).
Regarding claim 2, Yagyu (see, e.g., figs. 1-3C) shows wherein the plurality of terminals (e.g., plurality of leads (external terminals) LE) further includes a third terminal (e.g., third terminal of annotated fig. 2), wherein the plurality of wires (e.g., bonding wires BW) further includes a third wire (e.g., right-side wire connecting third terminal and second end portion electrode, see annotated fig. 2) connected to each of the second end portion electrode e.g., right-side electrode, see second end portion electrode of annotated fig. 2) and the third terminal (e.g., third terminal of annotated fig. 2).
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Annotated Fig. 2
Ishida (see, e.g., fig. 3), in a similar device to Yagyu in view of Suwa, teaches wherein a loop height (e.g., loop height of third wire 4c) of the first wire (e.g., third wire 4c) is greater than a loop height (e.g., loop height of second wire 4b) of the second wire (e.g., second wire 4b).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the superior loop height of Ishida within the third wire of Yagyu in view of Suwa further in view of Ishida, in order to improve electrical reliability and reduced defects within the device (see, e.g., paragraphs 144 of Ishida).
Regarding claim 3, Yagyu (see, e.g., figs. 1-3C) shows wherein, in plan view, the third surface (e.g., electrode-comprising surface of semiconductor chip SC) has:
A second side (e.g., third side S3) crossing the first side (e.g., first side S1);
A third side (e.g., fourth side S4) crossing the first side (e.g., first side S1) and opposite the second side (e.g., second side S3);
Wherein when 20% of a length of the first side (e.g., first side S1) is a first length (e.g., 20% ‘segment’ of first side S1); each of a distance between the first non-end portion electrode (e.g., first non-end portion electrode of annotated fig. 1) and the second side (e.g., third side S3) and distance between the first non-end portion electrode (e.g., first non-end portion electrode of annotated fig. 1) and the third side (e.g., fourth side S4) is larger (e.g., note that the first non-end portion electrode is configured substantially equally symmetrically between the second side and third side, halfway through the length of the first side, hence the distance between the first non-end portion electrode and both the second side and third side is substantially equal or close to 50% the first side S1) than the first length (e.g., 20% ‘segment’ of first side S1);
The current embodiment of Yagyu fails to explicitly state a distance between the first end portion electrode and the second side is less than the first length and a distance between the second end portion electrode and the third side is less than the first length.
However, note that Yagyu (see, e.g., fig. 1) shows the distance between the first end portion electrode and the second side is substantially small, well within the length of 20% the first side.
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Annotated Fig. 3
In addition, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to configure the end portion electrodes substantially close (less than the first length) to the sides of the semiconductor chip, in order to achieve the expected result of utilizing additional semiconductor chip space for electrodes or altering the electrode arrangement layout as necessary, and the exact distance between the end electrodes and the edge of the semiconductor chip becomes a design choice based on the layout and performance/connectivity requirements.
Regarding claim 11, Yagyu (see, e.g., figs. 1-3C) shows wherein each of the plurality of wires (e.g., bonding wires BW) includes: a ball portion (e.g., ball part BWa) connected to any one of the plurality of electrodes (e.g., plurality of electrode pads BP); and a standing portion (e.g., core part BWb) connected to the ball portion (e.g., ball part BWa) and extended upward of the semiconductor chip (e.g., semiconductor chip SC), and wherein when an angle formed by a portion (e.g., bent portion, see fig. 3C), which is located between the ball portion (e.g., ball part BWa) and the first side of the third surface (e.g., electrode-comprising surface of semiconductor chip SC) of the semiconductor chip (e.g., semiconductor chip SC) and the standing portion (e.g., core part BWb) is defined as a neck angle (see, e.g., paragraph 60 “Therefore, the bending angle of each core part of the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 is larger than the bending angle of each core part of the second wire W2, the fourth wire W4, the sixth wire W6, and the eighth wire W8.”), a neck angle (e.g., aforementioned bending angle) of the first wire (e.g., left-side wire of annotated fig. 1, note this is also W1 of fig. 1) is greater than 90 degrees (see, e.g., fig. 3C).
While Yagyu (see, e.g., fig. 3C), fails to explicitly show the neck angle of the first wire is greater than a neck angle of the second wire, Yagyu does show alternate neck portion angles between two groups of wires (see, e.g., paragraph 60 “Therefore, the bending angle of each core part of the first wire W1, the third wire W3, the fifth wire W5, and the seventh wire W7 is larger than the bending angle of each core part of the second wire W2, the fourth wire W4, the sixth wire W6, and the eighth wire W8.”), and the first wire (e.g., left-side wire of annotated fig. 1, note this is also W1) comprises the larger angle (see, e.g., paragraph 60).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second wire to the smaller angle, since only two configurations of wire angles are presented, i.e., the first core part bending angle or the second core part bending angle (see figs. 3A-3C), and since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as long as the wires are arranged as shown to connect the terminal to the electrode, as already suggested by Yagyu. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yagyu in view of Suwa further in view of Ishida and Ishii (US 20150115269 A1).
Regarding claim 4, Yagyu (see, e.g., figs. 1-3C) shows wherein the plurality of wires (e.g., bonding wires BW) includes: A plurality of first row wires (e.g., plurality of bonding wires BW connected to plurality of terminals LE and plurality of first row electrodes, see annotated fig. 1) connected to each of any ones of the plurality of first row electrodes (e.g., plurality of first row electrodes, see annotated fig. 1) and any ones of the plurality of terminals (e.g., plurality of terminals LE);
However, Yagyu in view of Suwa further in view of Ishida fails to teach wherein the plurality of electrodes includes a plurality of second row electrodes arranged along the first side of the semiconductor chip and arranged far away from the first side than the plurality of first row electrodes, any ones of the plurality of wires being connected with the plurality of second row electrodes, wherein the plurality of wires includes: a plurality of second row wires connected to each of any ones of the plurality of second row electrodes and any ones of the plurality of terminals, respectively, and wherein a loop height of each of the plurality of second row wires is greater than a loop height of the second wire.
Ishii (see, e.g., figs. 1-2), in a similar device to Yagyu in view of Suwa further in view of Ishida, teaches a plurality of electrodes includes a plurality of first row electrodes (e.g., electrode pads PD2) and a plurality of second row electrodes (e.g., electrode pads PD3), wherein a loop height of each of the plurality of second row wires (e.g., wires connected to second row electrodes) is greater (see, e.g., fig. 1) than a loop height of the second wire (e.g., wire connected to center electrode in first row of electrodes, see fig. 1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the plurality of second row electrode configuration of Ishii within the device and first plurality of row electrodes of Yagyu in view of Suwa further in view of Ishida, in order to achieve the expected result of enhancing the electrical performance and electrode density within the device, as well as including the superior loop height configuration within the plurality of second row wires in order to achieve the expected result of providing wire height for extending the connection to a farther distance. In addition, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to duplicate the plurality of first row electrodes and connecting wires directly beneath the first row of electrodes, improving electrode density within the configuration as desired, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. Note that with the duplicated electrode configuration, the wires connecting the terminals and electrode pads (configured beneath the first row of electrodes, hence farther away from the terminals than the first row of electrodes) would yield a greater loop height within the plurality of second row wires for the aforementioned reasons above.
Regarding claim 5, Ishii (see, e.g., figs. 1-2) teaches wherein the loop height of each of the plurality of second row wires (e.g., BW of PD3) is equal to each other (see, e.g., fig. 1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the equal loop height of Ishii within the second row wires of Yagyu in view of Suwa further in view of Ishida and Ishii, in order to achieve the expected result of providing a consistent electrical performance/profile due to the uniform height across the second row wires within the device.
Regarding claim 6, Ishii (see, e.g., figs. 1-2) teaches wherein the loop height of each of the plurality of second row wires (e.g., BW of PD3) is equal to each other (see, e.g., fig. 1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the equal loop height of Ishii within the plurality of second row wires of Yagyu in view of Suwa further in view of Ishida and Ishii, in order to achieve the expected result of providing a consistent electrical performance/profile due to the uniform height across the plurality of second row wires and first wire (corner wire) within the device. In addition, note that the duplicated electrode and wire configuration results in a wire configuration within the plurality of second row wires comprising substantially similar characteristics, including loop height.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yagyu in view of Suwa further in view of Ishida, Ishii, and Tashiro (US 20120018859 A1).
Regarding claim 7, Yagyu (see, e.g., figs. 1-3C) shows wherein the plurality of terminals (e.g., plurality of terminals LE) includes:
A plurality of first row terminals (e.g., plurality of terminals LE on top side of fig. 1, connected to first pad group G1) arranged in a first direction (e.g., horizontal direction), wherein the plurality of first row wires (e.g., plurality of bonding wires BW connected to plurality of terminals LE and plurality of first row electrodes, see annotated fig. 1) is connected to the plurality of first row terminals (e.g., plurality of terminals LE on top side of fig. 1, connected to first pad group G1), respectively.
Yagyu in view of Suwa further in view of Ishida and Ishii, however, fails to teach a plurality of second row terminals arranged in the first direction and arranged farther away from the semiconductor chip than the plurality of first row terminals, wherein the plurality of second row wires is connected to the plurality of second row terminals, respectively.
Tashiro (see, e.g., fig. 19), in a similar device to Yagyu in view of Suwa further in view of Ishida and Ishii, teaches a plurality of second row terminals (e.g., plurality of second row terminals in annotated fig. 4 below) arranged in a first direction (e.g., horizontal direction) and arranged farther away from a semiconductor chip (e.g., chip 3) than a plurality of first row terminals (e.g., plurality of first row terminals in annotated fig. 4 below), wherein a plurality of second row wires (e.g., plurality of wires 6) is connected to the plurality of second row terminals (e.g., plurality of second row terminals in annotated fig. 4 below), respectively.
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Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the plurality of second row terminals and exclusive first row of terminals to first row of wires and second row of terminals to second row of wires of Tashiro within the device of Yagyu in view of Suwa further in view of Ishida and Ishii, in order to achieve the expected result of providing an individual terminal and wire connection for every electrode within the plurality of rows of electrodes, enhancing the reliability of the device by isolating the connectivity setups so that a failure of a terminal would result in the failure of its one corresponding electrode, as opposed to the failure of a plurality of electrodes.
Yagyu (see, e.g., figs. 1-3C) shows wherein the plurality of first row electrodes (e.g., plurality of electrodes BP in annotated fig. 1 above) further includes a first corner portion electrode (see, e.g., annotated fig. 5) arranged next to the first end portion electrode (e.g., left-most electrode of electrode row of annotated fig. 1), wherein the plurality of wires (e.g., bonding wires BW) includes a fourth wire (see, e.g., annotated fig. 5) connected to each of the first corner portion electrode (see, e.g., annotated fig. 5) and a fourth terminal (see, e.g., annotated fig. 5) of the plurality of terminals (e.g., plurality of terminals LE).
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Ishida (see, e.g., fig. 3) teaches wherein a loop height (e.g., loop height of third wire 4c) of the first wire (e.g., third wire 4c) is greater than a loop height (e.g., loop height of second wire 4b) of the second wire (e.g., second wire 4b).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the superior loop height of Ishida within the fourth wire of Yagyu in view of Suwa further in view of Ishida and Ishii, in order to improve electrical reliability and reduced defects within the device (see, e.g., paragraphs 144 of Ishida). These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yagyu in view of Suwa further in view of Ishida, Ishii, Tashiro, and Milton (US 20180005980 A1).
Regarding claim 9, Yagyu in view of Suwa further in view of Ishida, Ishii, and Tashiro fails to teach wherein the loop height of the fourth wire is smaller than the loop height of each of the plurality of second row wires, and greater than the loop height of the second wire.
Milton (see, e.g., figs. 6A-6B), in a similar device to Yagyu in view of Suwa further in view of Ishida, Ishii, and Tashiro, teaches a loop height (see, e.g., fig. 6B) of a wire (e.g., wire loop 610) is smaller than a loop height of a second wire (e.g., wire loop 600) and greater than a loop height of a third wire (e.g., wire loop 620).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the intermediate height configuration of the wire of Milton within the loop height relationship of the fourth wire - plurality of second row wires and second wire of Yagyu in view of Suwa further in view of Ishida, Ishii, and Tashiro, in order to prevent the fourth wire from potentially interfering from the plurality of second row wires extending from behind and above it while simultaneously being configured above and away from interfering with the second wire laterally adjacent to it, adopting an intermediate profile and reducing the chance of wire interference within the device.
Regarding claim 10, Yagyu (see, e.g., figs. 1-3C) shows wherein the plurality of wires (e.g., bonding wires BW) extend backward away from the terminal in a cross section (see, e.g., fig. 3C).
Tashiro (see, e.g., fig. 19) teaches a plurality of second row electrodes (e.g., electrode pads 4 arranged farther from terminals/chip edge) configured substantially closely to a plurality of first row electrodes (e.g., electrode pads 4 arranged closer to terminals/chip edge).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the substantially close electrode configuration of Tashiro within the device of Yagyu in view of Suwa further in view of Ishida, Ishii, Tashiro, and Milton, in order to achieve the expected result of increasing electrode density/remaining chip space within the device as desired. Note that since the fourth wire of Yagyu comprises an embodiment in which it extends backward, tightly packed rows of electrodes would result in the bent portion of the fourth wire crossing at least a portion of this plurality of second row electrodes.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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