DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication 20220238672) in view of Choi et al (US Publication 20090096014).
Regarding claim 1, Lee teaches a vertical NAND flash memory device comprising:
a plurality of cell arrays (Fig. 1, 190), each of the plurality of cell arrays comprising:
a channel layer (Fig. 2, 170);
a charge trap layer provided on the channel layer (Fig. 2, 150), the charge trap layer comprising:
a plurality of nanocrystals provided in the matrix (Fig. 2, 152), the plurality of nanocrystals comprising nitride (para 78); and
a plurality of gate electrodes provided on the charge trap layer (Fig. 2, 130)
Lee does not specifically teach a matrix comprising amorphous metal oxynitride. It is noted that Lee does teach a charge trap layer as follows: Fig. 2, 150 with base material 151, para 74 amorphous, para 78-80 where the nanostructures of HfO and base AlN results in an oxynitride of HfAlON).
Choi teaches a matrix comprising amorphous metal oxynitride (Fig. 3, matrix 140 of charge trap layer 150, para 53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lee to include a matrix comprising amorphous metal oxynitride as taught by Choi in order to provide higher permittivity and trap energy thus improving the reliability and operability of the device.
Regarding claim 2, Lee as modified teaches the limitations of claim 1 upon which claim 2 depends.
Lee teaches wherein the plurality of nanocrystals are spatially separated from each other in the matrix (para 83).
Regarding claim 3, Lee as modified teaches the limitations of claim 1 upon which claim 3 depends.
Lee teaches wherein the matrix further comprising metal oxynitride having a permittivity greater than a permittivity of silicon nitride (para 78, GaN has greater permittivity than SiN).
Regarding claim 4, Lee as modified teaches the limitations of claim 3 upon which claim 4 depends.
Lee does not specifically teach wherein the matrix further comprises at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON.
Choi teaches wherein the matrix further comprises at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON (para 53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lee to include a matrix comprising AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON as taught by Choi in order to provide higher permittivity and trap energy thus improving the reliability and operability of the device.
Regarding claim 5, Lee as modified teaches the limitations of claim 1 upon which claim 5 depends.
Lee teaches wherein each of the plurality of nanocrystals comprises semiconductor nitride having a bandgap greater than 1 eV and less than a bandgap of a material of the matrix (para 7, 10).
Regarding claim 6, Lee as modified teaches the limitations of claim 5 upon which claim 6 depends.
Lee teaches wherein each of the plurality of nanocrystals comprises at least one of AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN (para 78, GaN).
Regarding claim 7, Lee as modified teaches the limitations of claim 1 upon which claim 7 depends.
Lee teaches wherein each of the plurality of nanocrystals has a size of about 0.5 nm to about 5 nm (para 82).
Regarding claim 8, Lee as modified teaches the limitations of claim 7 upon which claim 8 depends.
Lee teaches wherein each of the plurality of nanocrystals has a size of about 1 nm to about 3 nm (para 82).
Regarding claim 9, Lee as modified teaches the limitations of claim 1 upon which claim 9 depends.
Lee teaches wherein the plurality of nanocrystals are formed by heat treating the amorphous metal oxynitride of the matrix at a heat treatment temperature (para 109).
Furthermore, the present claim is drawn to a device, thus the method of forming the plurality of nanocrystals by heat treating does not patentably distinguish the claimed invention from that of the invention of Lee.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Regarding claim 10, Lee as modified teaches the limitations of claim 9 upon which claim 10 depends.
Lee does not specifically teach wherein the heat treatment temperature of the amorphous metal oxynitride is about 900 °C to about 1300 °C.
Furthermore, the present claim is drawn to a device, thus the method of heat treating does not patentably distinguish the claimed invention from that of the invention of Lee.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Choi teaches wherein the heat treatment temperature of the amorphous metal oxynitride is about 900 °C to about 1300 °C (para 74).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lee to include the heat treatment temperature as taught by Choi in order to further refine the manufacturing process of the device.
Regarding claim 11, Lee as modified teaches the limitations of claim 1 upon which claim 11 depends.
Lee teaches wherein the plurality of nanocrystals are buried in the matrix (Fig. 2, 152 within 151).
Regarding claim 12, Lee as modified teaches the limitations of claim 1 upon which claim 12 depends.
Lee teaches wherein one or more of the plurality of nanocrystals are provided in a boundary between the matrix and a layer adjacent to the matrix (Fig. 2, 152 in boundary between 151 and layers 140/160).
Regarding claim 13, Lee as modified teaches the limitations of claim 1 upon which claim 13 depends.
Lee teaches wherein each of the plurality of cell arrays is vertically provided to extend on a substrate (Fig. 1, 190 extends vertically from 110).
Regarding claim 14, Lee as modified teaches the limitations of claim 13 upon which claim 14 depends.
Lee teaches further comprises a channel hole extending in a direction perpendicular to the substrate is formed inside the channel layer (para 7).
Regarding claim 15, Lee as modified teaches the limitations of claim 14 upon which claim 15 depends.
Lee teaches wherein an inside of the channel hole is filled with an insulating layer (Fig. 2, 180).
Regarding claim 16, Lee as modified teaches the limitations of claim 14 upon which claim 16 depends.
Lee teaches wherein each of the channel layer and the charge trap layer is formed in a cylindrical shape surrounding the channel hole (para 71, 90).
Regarding claim 17, Lee as modified teaches the limitations of claim 16 upon which claim 17 depends.
Lee teaches wherein the plurality of gate electrodes are spaced apart from each other in a direction perpendicular to the substrate (Fig. 1, 130 spaced apart in direction perpendicular to 110), and wherein each of the plurality of gate electrodes surrounds the charge trap layer (Fig. 1 and 2, 130 surrounds 150).
Regarding claim 18, Lee as modified teaches the limitations of claim 16 upon which claim 18 depends.
Lee teaches further comprises a tunneling dielectric layer provided between the channel layer and the charge trap layer (Fig. 2, 160 between 170 and 150).
Regarding claim 19, Lee as modified teaches the limitations of claim 16 upon which claim 19 depends.
Lee teaches further comprises a barrier dielectric layer provided between the charge trap layer and each of the plurality of gate electrodes (Fig. 2, 140).
Regarding claim 20, Lee teaches an electronic apparatus comprising:
a plurality of cell arrays (Fig. 1, 190),
each of the plurality of cell arrays comprising:
a channel layer (Fig. 2, 170);
a charge trap layer provided on the channel layer (Fig. 2, 150), the charge trap layer comprising:
a plurality of nanocrystals provided in the matrix (Fig. 2, 152), the plurality of nanocrystals comprising nitride (para 78); and
a plurality of gate electrodes provided on the charge trap layer (Fig. 1/2, 130).
Lee does not specifically teach a matrix comprising amorphous metal oxynitride. It is noted that Lee does teach a charge trap layer as follows: Fig. 2, 150 with base material 151, para 74 amorphous, para 78-80 where the nanostructures of HfO and base AlN results in an oxynitride of HfAlON).
Choi teaches a matrix comprising amorphous metal oxynitride (Fig. 3, matrix 140 of charge trap layer 150, para 53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lee to include a matrix comprising amorphous metal oxynitride as taught by Choi in order to provide higher permittivity and trap energy thus improving the reliability and operability of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Bhattacharyya (US Publication 20070052011) – Scalable multi-functional and multi-level nano-crystal non-volatile memory device.
Bhattacharyya (US Publication 20060261401) – Novel low power non-volatile memory and gate stack.
Levy et al (US Publication 20180366563) – Oxide-nitride-oxide stack having multiple oxynitride layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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