Prosecution Insights
Last updated: July 17, 2026
Application No. 18/439,349

PAD AND PACKAGE INCLUDING SAME

Non-Final OA §102§103
Filed
Feb 12, 2024
Priority
Mar 24, 2023 — CN 202310301066.3
Examiner
HUTSON, NICHOLAS LELAND
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
11m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
15 granted / 25 resolved
-8.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
11 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
84.5%
+44.5% vs TC avg
§102
14.1%
-25.9% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nam (US Publication 20240250010). Regarding claim 1, Nam teaches a pad comprising: a terminal portion having a first surface and a second surface opposite to the first surface (Fig. 8, 121 top and bottom surface); and a curved concave portion formed in one of the first surface and the second surface (Fig. 8, 121 concave on top surface, para 94 "concave portion"), wherein the curved concave portion is configured to clad a portion of a connecting conductor (Fig. 8, 121 clads portion of connection part 212 solder ball, para 191). Regarding claim 2, Nam teaches the limitations of claim 1 upon which claim 2 depends. Nam teaches wherein the curved concave portion has a concave spherical surface or a concave ellipsoidal surface (para 114, "circular shape", para 115, "oval shape"). Regarding claim 3, Nam teaches the limitations of claim 1 upon which claim 3 depends. Nam teaches wherein the terminal portion has a prism shape or a cylindrical shape (para 191). Regarding claim 4, Nam teaches the limitations of claim 1 upon which claim 4 depends. Nam teaches wherein the curved concave portion has a depth less than or equal to a height of the terminal portion (Fig. 8, depth of concave in 121 less than or equal to height of terminal portion of 121, para 171). Claims 5-10 and 12-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US Publication 20160049377). Regarding claim 5, Kim teaches a package comprising: a substrate comprising a first connection area (Fig. 3B, substrate 110 with first connection area 112); a chip body comprising a second connection area (Fig. 3B, chip body 150 with second connection area 152); a substrate pad disposed on the first connection area (Fig. 3B, 114); a chip pad disposed on the second connection area (Fig. 3B, 153); and a connecting conductor connecting the substrate pad and the chip pad (Fig. 3B, 160), wherein the chip pad comprises: a first terminal portion having a first surface and a second surface opposite to the first surface (Fig. 3B, top and bottom surfaces of 153); and a first curved concave portion formed in one of the first surface and the second surface (Fig. 3B, curved surface of 153), and wherein the first curved concave portion clads a first portion of the connecting conductor (Fig. 3B, curved surface of 153 clads 160). Regarding claim 6, Kim teaches the limitations of claim 5 upon which claim 6 depends. Kim teaches wherein the substrate pad comprises: a second terminal portion having a third surface and a fourth surface opposite to the third surface (Fig. 3B, top and bottom surfaces of 112); and a second curved concave portion formed in one of the third surface and the fourth surface (Fig 3B, curved surface of 114, para 50), wherein the second curved concave portion clads a second portion of the connecting conductor (Fig. 3B, curved surface of 114 clads 160). Regarding claim 7, Kim teaches the limitations of claim 5 upon which claim 7 depends. Kim teaches wherein the connecting conductor comprises a solder ball (para 47). Regarding claim 8, Kim teaches the limitations of claim 6 upon which claim 8 depends. Kim teaches wherein the substrate pad and the chip pad form a cladding cavity, and wherein the cladding cavity completely clads the connecting conductor (Fig. 3B, 114 and 153 clad 160 after solder process). Regarding claim 9, Kim teaches the limitations of claim 6 upon which claim 9 depends. Kim teaches wherein the substrate pad and the chip pad form a cladding cavity, and wherein the cladding cavity partially clads the connecting conductor (Fig. 3B, 114 and 153 clad 160 after solder process). Regarding claim 10, Kim teaches the limitations of claim 6 upon which claim 10 depends. Kim teaches wherein a volume of the first portion of the connecting conductor is the same as a volume of the second portion of the connecting conductor (Fig. 3B, 114 and 153 volume the same). Regarding claim 12, Kim teaches the limitations of claim 6 upon which claim 12 depends. Kim teaches wherein the package is configured as chip packaging for a camera (para 92). Regarding claim 13, Kim teaches an apparatus comprising: a first pad comprising a first concave surface configured to wrap around a connecting conductor (Fig. 3B, 153 with concave surface that wraps around 160). Regarding claim 14, Kim teaches the limitations of claim 13 upon which claim 14 depends. Kim teaches further comprising a second pad comprising a second concave surface configured to wrap around the connecting conductor (Fig. 3B, 114 with concave surface that wraps around 160), wherein the first concave surface faces toward the second concave surface (Fig. 3B concave surfaces of 153 and 114 face each other). Regarding claim 15, Kim teaches the limitations of claim 14 upon which claim 15 depends. Kim teaches further comprising a chip body, wherein the first pad is disposed on the chip body (Fig. 3B, chip body 150 with pad 153). Regarding claim 16, Kim teaches the limitations of claim 15 upon which claim 16 depends. Kim teaches further comprising a substrate, wherein the second pad is disposed on the substrate (Fig. 3B, substrate 110 with pad 114). Regarding claim 17, Kim teaches the limitations of claim 16 upon which claim 17 depends. Kim teaches further comprising the connecting conductor disposed between the first pad and the second pad (Fig. 3B, 160 between 153 and 114). Regarding claim 18, Kim teaches the limitations of claim 17 upon which claim 18 depends. Kim teaches wherein the connecting conductor comprises a convex surface (Fig. 3B, convex surface of solder balls 160). Regarding claim 19, Kim teaches the limitations of claim 13 upon which claim 19 depends. Kim teaches wherein the apparatus is configured as chip packaging for a camera (para 92). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Publication 20160049377) in view of Nam (US Publication 20240250010). Regarding claim 11, Kim teaches the limitations of claim 6 upon which claim 11 depends. Kim does not specifically teach wherein a volume of the first portion of the connecting conductor is different from a volume of the second portion of the connecting conductor. Nam teaches wherein a volume of the first portion of the connecting conductor is different from a volume of the second portion of the connecting conductor (Fig. 8, cavity containing 211 between 230 and 121 have different volumes). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include a volume of the first portion of the connecting conductor is different from a volume of the second portion of the connecting conductor as taught by Nam in order to improve the reliability and operability of the device. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US Publication 20220399296) – Semiconductor package. Yen et al (US Publication 20210384152) – Semiconductor device with conductive pad. Tsai et al (US Publication 20230105359) – Integrated Circuit Packages. Lee et al (US Publication 20130320523) – Semiconductor Device and Method of Reflow Soldering for Conductive Column Structure in Flip Chip Package. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS LELAND HUTSON/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Feb 12, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
77%
With Interview (+16.7%)
3y 4m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allowance rate.

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