Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Status of the Claims Claims 1-2 0 are pending. Action on merits of 1-2 0 as follows. Information Disclosure Statement The information disclosure statement ( IDS) submitted on May 15 th , 2025 has been considered by the examiner. Drawings The drawings filed on 02/12/2024 are acceptable. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1 , 5 - 9, 11, 15 are rejected under 35 U.S.C. 102( a ) (1) as being clearly anticipated by Otsuka (US 2004/0184219 , hereinafter as Otsu ‘219 ). Regarding Claim 1 , Otsu ‘219 teaches a package comprising: a substrate (Fig. 13, (98); [0113]) comprising a first surface and a second surface, wherein the substrate further comprises: at least one dielectric layer ( e.g. Aluminum nitride; [0113] ) ; and a plurality of interconnects (182, 183, 184; [0143]) ; an integrated device (IC chip (21); [0095]) coupled to the first surface of the substrate through at least a first plurality of solder interconnects (22 and 97; [0125] ; and a passive device (capacitor (101); [0144) coupled to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via (94; [0145]) . Regarding Claim 1 1 , Otsu ‘219 teaches a method for fabricating a package comprising: providing a substrate (Fig. 13, (98); [0113]) comprising a first surface and a second surface, wherein the substrate further comprises: at least one dielectric layer (e.g. Aluminum nitride; [0113]) ; and a plurality of interconnects (182, 183, 184; [0143]) ; coupling an integrated device (IC chip (21); [0095]) to the first surface of the substrate through at least a first plurality of solder interconnects (22 and 97; [0125] ; and coupling a passive device (capacitor (101); [0144) to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via (94; [0145]) . Regarding Claim s 5 and 15 , Otsu ‘219 teaches the substrate is coupled to a board (41; [0094]) through a third plurality of solder interconnects (100, 107; [0117]) , and wherein the passive device (101) is coupled to the board through a fourth plurality of solder interconnects (100, 107) (see Fig. 13) . Regarding Claim s 6 and 16 , Otsu ‘219 teaches an electrical path between the integrated device and the board comprises ( i ) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, (iii) a solder interconnect from the second plurality of solder interconnects, (iv) at least one through substrate via from the passive device, and/or (v) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13) . Regarding Claims 7 and 17 , Otsu ‘219 teaches an electrical path between the integrated device and the board comprises ( i ) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, and/or (iii) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13) . Fig. 13 ( Otsu ‘219 ) Regarding Claim s 8 and 18 , Otsu ‘219 teaches a first electrical path between the integrated device and the board comprises ( i ) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, (iii) a solder interconnect from the second plurality of solder interconnects, (iv) at least one through substrate via from the passive device, and/or (v) a solder interconnect from the fourth plurality of solder interconnects, and wherein a second electrical path between the integrated device and the board comprises ( i ) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, and/or (iii) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13) . Regarding Claim s 9 and 19 , Otsu ‘219 teaches the passive device (101) is part of a power distribution network for the integrated device (see Fig. 13) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 -4, 10 , 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Otsu ‘219 as applied to claim 1 above , and further in view of Kim (US 2021/0098567 , hereinafter as Kim ‘567 ). Regarding Claim s 2 and 12 , Otsu ‘219 is shown to teach all the features of the claim with the exception of explicitly the limitations: “ the passive device comprises a trench capacitor device ”. However, Kim ‘567 teaches a trench capacitor device (Fig. 2, (200); [0031]) . Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the in vention to modify Otsu ‘219 by having a trench capacitor device for the purpose of improve the performance of the integrated device (see para. [00 29 ]) as suggested by Kim ‘567 . Regarding Claim s 3 and 13 , Kim ‘567 teaches the trench capacitor device (200; [0031]) comprises a passive device substrate (202; [0031]) , and wherein the at least one through substrate via (Fig. 7, (7 12 ); [00 48 ]) extends through the passive device substrate (see Fig. 7) . Regarding Claim s 4 and 14 , Kim ‘567 teaches the passive device comprises a plurality of trench capacitors (Figs. 3-4, (200a-h); [0036]) . Regarding Claim s 10 and 20 , Kim ‘567 teaches the passive device comprises: a passive device substrate (202) ; a plurality of trench capacitors (200) located at least partially in the passive device substrate (202) ; and a first metallization portion (755; [0053]) located on a first surface of the passive device substrate, wherein the at least one through substrate via (7 1 2) extends through the passive device substrate (see Fig. 7) , and wherein the at least one through substrate via (712) is coupled to the first metallization portion (see Fig. 7) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices: Agawa et al. ( US 2023/0089615 A1 ) Lin et al. (US 201 9 /0 229180 A1) Jia et al. (US 20 19 /0 229181 A1) Fujii et al. (US 2019/0080849 A1 ) Voiron (US 2017/0104057 A1 ) For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. S ee MPEP 2141.02 VI. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DZUNG T TRAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571) 270-3911 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT M-F 8 AM-5PM . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on ( FILLIN "SPE Phone?" \* MERGEFORMAT 571) 272-1236 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. / DZUNG TRAN/ Primary Examiner, Art Unit 2893