Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-20 in the reply filed on June 26th, 2026, are acknowledged. Claims 1 and 11 have been amended. Claims 1-20 are pending.
Action on merits of 1-20 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 5-9, 11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Otsuka (US 2004/0184219, hereinafter as Otsu ‘219) in view of Yamamoto (US 2009/0255719, hereinafter as Yama ‘719).
Regarding Claim 1, Otsu ‘219 teaches a package comprising:
a substrate (Fig. 13, (98); [0113]) comprising a first surface and a second surface, wherein the substrate further comprises:
at least one dielectric layer (e.g. Aluminum nitride; [0113]); and
a plurality of interconnects (182, 183, 184; [0143]);
an integrated device (IC chip (21); [0095]) coupled to the first surface of the substrate through at least a first plurality of solder interconnects (22 and 97; [0125]; and
a passive device (capacitor (101); [0144) coupled to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via (94; [0145]).
Otsu ‘219 is shown to teach all the features of the claim with the exception of explicitly the limitations: “at least one through substrate via is not coplanar with any interconnect of the plurality of interconnects of the substrate”.
Yama ‘719 teaches the at least one through substrate via (Fig. 1, (131); [0066]) is not coplanar with any interconnect of the plurality of interconnects (42; [0059]) of the substrate (see Fig. 1). Examiner considers the conductor (42; [0069]) is an interconnect.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Otsu ‘219 by having at least one through substrate via is not coplanar with any interconnect of the plurality of interconnects of the substrate in order to provide a wiring board offering a secure and reliable electrical connection between the built-up layer and the ceramic chip to be embedded (see para. [0006]) as suggested by Yama ‘719.
Regarding Claim 11, Otsu ‘219 teaches a method for fabricating a package comprising:
providing a substrate (Fig. 13, (98); [0113]) comprising a first surface and a second surface, wherein the substrate further comprises:
at least one dielectric layer (e.g. Aluminum nitride; [0113]); and
a plurality of interconnects (182, 183, 184; [0143]);
coupling an integrated device (IC chip (21); [0095]) to the first surface of the substrate through at least a first plurality of solder interconnects (22 and 97; [0125]; and
coupling a passive device (capacitor (101); [0144) to the second surface of the substrate through at least a second plurality of solder interconnects, wherein the passive device comprises at least one through substrate via (94; [0145]).
Otsu ‘219 is shown to teach all the features of the claim with the exception of explicitly the limitations: “at least one through substrate via is not coplanar with any interconnect of the plurality of interconnects of the substrate”.
Yama ‘719 teaches the at least one through substrate via (Fig. 1, (131); [0066]) is not coplanar with any interconnect of the plurality of interconnects (42; [0059]) of the substrate (see Fig. 1). Examiner considers the conductor (42; [0069]) is an interconnect.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Otsu ‘219 by having at least one through substrate via is not coplanar with any interconnect of the plurality of interconnects of the substrate in order to provide a wiring board offering a secure and reliable electrical connection between the built-up layer and the ceramic chip to be embedded (see para. [0006]) as suggested by Yama ‘719.
Regarding Claims 5 and 15, Otsu ‘219 teaches the substrate is coupled to a board (41; [0094]) through a third plurality of solder interconnects (100, 107; [0117]), and wherein the passive device (101) is coupled to the board through a fourth plurality of solder interconnects (100, 107) (see Fig. 13).
Regarding Claims 6 and 16, Otsu ‘219 teaches an electrical path between the integrated device and the board comprises (i) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, (iii) a solder interconnect from the second plurality of solder interconnects, (iv) at least one through substrate via from the passive device, and/or (v) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13).
Regarding Claims 7 and 17, Otsu ‘219 teaches an electrical path between the integrated device and the board comprises (i) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, and/or (iii) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13).
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Fig. 13 (Otsu ‘219)
Regarding Claims 8 and 18, Otsu ‘219 teaches a first electrical path between the integrated device and the board comprises (i) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, (iii) a solder interconnect from the second plurality of solder interconnects, (iv) at least one through substrate via from the passive device, and/or (v) a solder interconnect from the fourth plurality of solder interconnects, and wherein a second electrical path between the integrated device and the board comprises (i) a solder interconnect from the first plurality of solder interconnects, (ii) at least one interconnect from the plurality of interconnects of the substrate, and/or (iii) a solder interconnect from the fourth plurality of solder interconnects (see Fig. 13).
Regarding Claims 9 and 19, Otsu ‘219 teaches the passive device (101) is part of a power distribution network for the integrated device (see Fig. 13).
Claims 2-4, 10, 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Otsu ‘219 and Yama ‘719 as applied to claim 1 above, and further in view of Kim (US 2021/0098567, hereinafter as Kim ‘567).
Regarding Claims 2 and 12, Otsu ‘219 and Yama ‘719 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the passive device comprises a trench capacitor device”.
However, Kim ‘567 teaches a trench capacitor device (Fig. 2, (200); [0031]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Otsu ‘219 and Yama ‘719 by having a trench capacitor device for the purpose of improve the performance of the integrated device (see para. [0029]) as suggested by Kim ‘567.
Regarding Claims 3 and 13, Kim ‘567 teaches the trench capacitor device (200; [0031]) comprises a passive device substrate (202; [0031]), and wherein the at least one through substrate via (Fig. 7, (712); [0048]) extends through the passive device substrate (see Fig. 7).
Regarding Claims 4 and 14, Kim ‘567 teaches the passive device comprises a plurality of trench capacitors (Figs. 3-4, (200a-h); [0036]).
Regarding Claims 10 and 20, Kim ‘567 teaches the passive device comprises: a passive device substrate (202); a plurality of trench capacitors (200) located at least partially in the passive device substrate (202); and a first metallization portion (755; [0053]) located on a first surface of the passive device substrate, wherein the at least one through substrate via (712) extends through the passive device substrate (see Fig. 7), and wherein the at least one through substrate via (712) is coupled to the first metallization portion (see Fig. 7).
Response to Arguments
Applicant’s arguments with respect to claims 1-20, filed on June 26th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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